1. A method of manufacturing a clip comprising the steps of:
forming the precursor of a clip from a material comprising a superelastic alloy which has an austenitic state and a martensitic state, said precursor having an annular body which is planar and having one or more tines which extend radially outwardly from said body;
inverting said precursor such that said tines extend radially inwardly; heating said precursor in its inverted configuration to cause said alloy to become austenitic; and quenching said heated precursor to form a clip which is austenitic.
2. The method of claim 1 wherein said alloy is nickel-titanium.
3. The method of claim 1 wherein said body comprises a plurality of looped elements.
4. The method of claim 1 wherein, after inversion, at least two tines are in side-by-side relationship.
5. The method of claim 1 wherein, after inversion, at least two tines are in over-and-under relationship.
6. The method of claim 1 wherein at least one tine is longer than a radially opposed tine.
7. The method of claim 1 wherein said forming step comprises cutting said precursor from a sheet of material comprising a superelastic alloy.
8. A method of manufacturing a clip comprising the steps of:
forming the precursor of a clip from a material comprising a superelastic alloy which has an austenitic state and a martensitic state, said precursor having an annular body which is planar and having one or more tines which extend radially inwardly from said body;
said precursor having a lateral dimension which is larger than that of the clip;
compressing said precursor in a radially inward direction to bring said tines closer together;
heating said precursor in its compressed configuration to cause said alloy to become austenitic; and
quenching said heated precursor to form a clip which is austenitic.
9. The method of claim 8 wherein said alloy is nickel titanium.
10. The method of claim 8 wherein said body comprises a plurality of looped elements.
11. The method of claim 9 wherein the nickel titanium has a grain orientation and at least two tines have a longitudinal dimension transverse to the grain orientation.
12. The method of claim 8 wherein, after compression, at least two tines are in side-by-side relationship.
13. The method of claim 8 wherein, after compressing said precursor, at least two tines are in over-and-under relationship.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor memory device having a self-refresh operation comprising:
a first circuit generating a first signal that specifies a first self-refresh cycle by a non-volatile circuit element provided in the semiconductor memory device;
a second circuit receiving a second signal that specifies a second self-refresh cycle via a terminal that is used in common to another signal; and
a third circuit generating a pulse signal having one of the first and second self-refresh cycles, said pulse signal being related to the self-refresh operation.
2. The semiconductor memory device as claimed in claim 1, wherein said third circuit comprises a counter, and one of the first and second signals is data related to a count value of said counter.
3. The semiconductor memory device as claimed in claim 1, wherein said third circuit comprises:
a count value setting circuit selecting one of count values respectively specified by the first and second signals; and
a counter operating in accordance with a selected one of the count values.
4. The semiconductor memory device as claimed in claim 1, wherein said third circuit selects one of the first and second signals in accordance with a test signal supplied outside of the semiconductor memory device.
5. The semiconductor memory device as claimed in claim 2, wherein said third circuit selects one of the first and second signals in accordance with a test signal supplied outside of the semiconductor memory device.
6. The semiconductor memory device as claimed in claim 3, wherein said third circuit selects one of the first and second signals in accordance with a test signal supplied from an outside of the semiconductor memory device.
7. The semiconductor memory device as claimed in claim 1, wherein said second circuit comprises a gate which outputs the second signal only when the semiconductor memory device receives a test signal supplied from an outside thereof.
8. The semiconductor memory device as claimed in claim 1, wherein said first circuit comprises a fuse.
9. The semiconductor memory device as claimed in claim 1, wherein said second circuit comprises a buffer.
10. The semiconductor memory device as claimed in claim 1, wherein the second signal includes an address signal.
11. The semiconductor memory device as claimed in claim 1, wherein said terminal receives the second signal from an outside of the semiconductor memory device.
12. The semiconductor memory device as claimed in claim 1, wherein the second signal comprises a plurality of address bits.
13. The semiconductor memory device as claimed in claim 1, wherein said first circuit comprises a plurality of fuses.