1. A semiconductor device comprising:
a substrate including isolation regions and active regions;
a high-k dielectric layer proximate the substrate, the high-k dielectric layer comprising a mixture formed by annealing at least one high-k material and at least one metal, the annealing to oxidize the metal; and
a gate electrode proximate the high-k dielectric layer,
wherein the high-k dielectric layer has a k value within a range of 30 to 70.
2. The semiconductor device of claim 1, wherein the mixture is formed by annealing a first high-k material layer and a first metal layer proximate the first high-k material layer.
3. The semiconductor device of claim 1, wherein the high-k dielectric layer has a thickness within a range of 20 \u212b to 100 \u212b.
4. The semiconductor device of claim 1, wherein the high-k material comprises one of Si3N4, Al2O3, Ta2O5, HfO2, TiO2, HfSiOx, ZrO2, ZrSiOx, La2O3, CeO2, Bi4Si2O12, WO3, Y2O3, LaAlO3, BST, PST, PZN, PZT, and PMN.
5. The semiconductor device of claim 4, wherein the metal comprises one of TiN, HfN, TaN, ZrN, and LaN.
6. A semiconductor device comprising:
a substrate including isolation regions and active regions;
a high-k dielectric layer proximate the substrate, the high-k dielectric layer comprising a mixture formed by annealing at least one high-k material and at least one metal, the annealing to oxidize the metal; and
a gate electrode proximate the high-k dielectric layer,
wherein the high-k dielectric layer comprises HfTaTiOc.
7. The semiconductor device of claim 6, wherein the high-k dielectric layer is incorporated with N.
8. A transistor comprising:
a gate electrode;
a high-k dielectric layer proximate the gate electrode, the high-k dielectric layer comprising a mixture formed by annealing a high-k material and a metal, the annealing to oxidize the metal; and
a substrate comprising an active region, the substrate proximate the high-k dielectric layer,
wherein the high-k dielectric layer has a k value greater than 30.
9. The transistor of claim 8, wherein the high-k material comprises one of Si3N4, Al2O3, Ta2O5, HfO2, TiO2, HfSiOx, ZrO2, ZrSiOx, La2O3, CeO2, Bi4Si2O12, WO3, Y2O3, LaAlO3, BST, PST, PZN, PZT, and PMN.
10. The transistor of claim 9, wherein the metal comprises one of TiN, HfN, TaN, ZrN, and LaN.
11. The transistor of claim 8, wherein the gate electrode comprises one of aluminum, polysilicon, TiN, TaN, HfN, RuN, WN, W, MoN, TaSiN, RuSiN, WSiN, HfSiN, and TiSiN.
12. A transistor comprising:
a gate electrode;
a high-k dielectric layer proximate the gate electrode, the high-k dielectric layer comprising a mixture formed by annealing a high-k material and a metal, the annealing to oxidize the metal; and
a substrate comprising an active region, the substrate proximate the high-k dielectric layer,
wherein the high-k dielectric layer comprises HfTaTiOx.
13. The transistor of claim 12, wherein the high-k dielectric layer is incorporated with N.
14. The transistor of claim 8, wherein the transistor is an NMOS transistor.
15. The transistor of claim 8, wherein the transistor is a PMOS transistor.
16. A semiconductor device comprising:
a substrate including isolation regions and active regions;
a high-k dielectric layer proximate the substrate, the high-k dielectric layer having a first k value and comprising a mixture formed by annealing at least a first layer of material having a second k value and a second layer of material having a third k value, the first k value greater than the second k value and the third k value; and
a gate electrode proximate the high-k dielectric layer,
wherein the first k value is greater than 30.
17. The semiconductor device of claim 16, wherein the first layer of material comprises a high-k material and the second layer of material comprises a metal.
18. The semiconductor device of claim 16, wherein the first layer of material comprises a high-k material and the second layer of material comprises a material that acts as a metal.
19. The semiconductor device of claim 16, wherein the high-k dielectric layer is incorporated with N.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An organic light emitting diode (OLED) display comprising:
a substrate;
a thin film transistor on the substrate;
a first insulation layer on the thin film transistor;
a second insulation layer on the first insulation layer, the second insulation layer having a first opening exposing a portion of the first insulation layer;
a first electrode electrically connected with the thin film transistor and contacting the second insulation layer and contacting the first insulation layer through the first opening;
a pixel defining layer disposed on the first electrode and having a second opening exposing a portion of the first electrode in a region corresponding to the first opening, the second opening being smaller than the first opening, wherein the pixel defining layer comprises a plurality of inclined surfaces forming the second opening;
an organic emission layer on the first electrode in a region corresponding to the second opening, the organic emission layer covering at least one of the plurality of inclined surfaces of the pixel defining layer; and
a second electrode on the organic emission layer in a region corresponding to the second opening.
2. The OLED display of claim 1, wherein at least one of the organic emission layer and the second electrode is disposed on fewer than all of the plurality of inclined surfaces.
3. The OLED display of claim 1, wherein the first electrode is a light reflective electrode and the second electrode is a light transmissive electrode.
4. The OLED display of claim 1, wherein the organic emission layer has a refractive index that is different from the refractive indexes of the first electrode, the pixel defining layer, and the second electrode.
5. The OLED display of claim 1, wherein the second opening is in a shape of a flat quadrangle, and
wherein the pixel defining layer forms the second opening and further comprises:
first and second inclined surfaces that are disposed opposite to each other; and
third and fourth inclined surfaces that are disposed opposite to each other.
6. The OLED display of claim 5, wherein the third inclined surface connects first ends of the first and second inclined surfaces, and the fourth inclined surface connects second ends of the first and second inclined surfaces.
7. The OLED display of claim 5, wherein the first and second inclined surfaces are longer than the third and fourth inclined surfaces.
8. The OLED display of claim 5, wherein the organic emission layer and the second electrode are disposed only on the third and fourth inclined surfaces among the first, second, third, and fourth inclined surfaces.
9. The OLED display of claim 5, wherein the second electrode is disposed only on the third and fourth inclined surfaces among the first, second, third, and fourth inclined surfaces.
10. The OLED display of claim 9, wherein the organic emission layer is disposed on the first, second, third, and fourth inclined surfaces.
11. The OLED display of claim 5, wherein the organic emission layer is disposed only on the third and fourth inclined surfaces among the first, second, third, and fourth inclined surfaces.
12. The OLED display of claim 11, wherein the second electrode is disposed on the first, second, third, and fourth inclined surfaces.