1. A photoelectric conversion apparatus comprising:
a semiconductor substrate of a first conduction type;
a first semiconductor region of the first conduction type;
a second semiconductor region of a second conduction type, which isolates the semiconductor substrate and the first semiconductor region from each other;
a pixel unit in which pixels are arranged two-dimensionally, each pixel including:
a photoelectric conversion unit with a third semiconductor region of the first conduction type having an impurity concentration higher than that of the first semiconductor region and a fourth semiconductor region of the second conduction type,
an amplifying transistor for readout signals from the photoelectric conversion unit, and
an element isolation region that electrically isolates an active region where the photoelectric conversion unit is arranged from an active region where the amplifying transistor is arranged;
a fifth semiconductor region of the second conduction type, which is arranged in the first semiconductor region along a side surface and a bottom surface of the element isolation region of each pixel; and
a sixth semiconductor region of the second conduction type, which is arranged between source and drain regions of an amplifying transistor of each pixel and is the second semiconductor region, in a region below a gate electrode of the amplifying transistor,
wherein a contact for supplying a reference voltage to the sixth semiconductor region, via the fifth semiconductor region, is arranged in the active region where a photoelectric conversion unit of each pixel is arranged,
wherein the contact includes a plug for supplying the reference voltage, and a seventh semiconductor region of the second conduction type to which the plug is electrically connected, and
wherein an eighth semiconductor region of the second conduction type, which has an impurity concentration lower than that of the seventh semiconductor region, is arranged between the seventh semiconductor region and the third semiconductor region.
2. The photoelectric conversion apparatus according to claim 1, wherein the fifth semiconductor region and the second semiconductor region are electrically connected to each other.
3. The photoelectric conversion apparatus according to claim 1, wherein the sixth semiconductor region and the eighth semiconductor region are formed in a same step.
4. The photoelectric conversion apparatus according to claim 1, wherein a plurality of pixels are used as a unit block, and a contact is arranged for each unit block.
5. The photoelectric conversion apparatus according to claim 4, wherein, in the plurality of pixels included in the unit block, the fourth semiconductor region is arranged so as to be continuous with the fourth semiconductor region of an adjacent pixel, and the contact supplies a reference voltage via the fourth semiconductor region to the sixth semiconductor regions of the plurality of pixels included in the unit block.
6. The photoelectric conversion apparatus according to claim 1,
wherein primary color filters are arranged to correspond to the pixels of the pixel unit, and
wherein the contact is arranged in a pixel where a blue filter among the primary color filters is arranged.
7. A photoelectric conversion apparatus comprising:
a semiconductor substrate of a first conduction type;
a first semiconductor region of the first conduction type;
a second semiconductor region of a second conduction type, which isolates the semiconductor substrate and the first semiconductor region from each other;
a pixel unit in which unit cells are arranged two-dimensionally, each unit cell including:
a plurality of photoelectric conversion units, each photoelectric conversion unit including a third semiconductor region of the first conduction type having an impurity concentration higher than that of the first semiconductor region and a fourth semiconductor region of the second conduction type,
an amplifying transistor for reading out signals from the plurality of photoelectric conversion units, and
an element isolation region that electrically isolates an active region where each of the plurality of photoelectric conversion units is arranged from an active region where the amplifying transistor is arranged;
a fifth semiconductor region of the second conduction type, which is arranged in the first semiconductor region along a side surface and a bottom surface of the element isolation region; and
a sixth semiconductor region of the second conduction type, which is arranged between source and drain regions of the amplifying transistor and the second semiconductor region, in a region below a gate electrode of the amplifying transistor,
wherein a contact for supplying a reference voltage to the sixth semiconductor region via the fifth semiconductor region is arranged in an active region where at least one of the plurality of photoelectric conversion units is arranged,
wherein the contact includes a plug for supplying the reference voltage, and a seventh semiconductor region of the second conduction type to which the plug is electrically connected, and
wherein an eighth semiconductor region of the second conduction type, which has an impurity concentration lower than that of the seventh semiconductor region, is arranged between the seventh semiconductor region and the third semiconductor region.
8. A photoelectric conversion apparatus according to claim 1, wherein the photoelectric conversion apparatus is incorporated in an imaging system that includes a signal processing circuit configured to process a signal from the photoelectric conversion apparatus.
9. The photoelectric conversion apparatus according to claim 7, wherein the fifth semiconductor region and the second semiconductor region are electrically connected to each other.
10. The photoelectric conversion apparatus according to claim 7, wherein the sixth semiconductor region and the eighth semiconductor region are formed in a same step.
11. The photoelectric conversion apparatus according to claim 7, wherein one contact is arranged for a plurality of unit cells.
12. The photoelectric conversion apparatus according to claim 7,
wherein primary color filters are arranged to correspond to respective photoelectric conversion units, and
wherein the contact is arranged in a photoelectric conversion unit on which a blue filter among the primary color filters is arranged.
13. A photoelectric conversion apparatus according to claim 7, wherein the photoelectric conversion apparatus is incorporated in an imaging system that includes a signal processing circuit configured to process a signal from the photoelectric conversion apparatus.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A package structure module with high density electrical connections, comprising:
a first structure;
a second structure having a height higher than that of the first structure, wherein the second structure has a plurality of second open grooves formed on a lateral wall thereof and close to the first structure; and
a plurality of conductive structures respectively traverse the second open grooves in order to make the conductive structures electrically connect between the first structure and the second structure.
2. The package structure module as claimed in claim 1, wherein the first structure has a plurality of first open grooves formed on a lateral wall thereof and respectively facing the second open grooves, and the conductive structures respectively traverse the first open grooves.
3. The package structure module as claimed in claim 1, wherein each second open groove has a depth of between 50 \u03bcm and 100 \u03bcm.
4. The package structure module as claimed in claim 2, wherein each first open groove has a depth of between 50 \u03bcm and 100 \u03bcm.
5. The package structure module as claimed in claim 1, wherein the first structure is a drive IC structure, and the second structure is an LED array structure.
6. The package structure module as claimed in claim 1, wherein the first structure is an LED array structure, and the second structure is a drive IC structure.
7. The package structure module as claimed in claim 1, further comprising a substrate having at least two inputoutput pads, wherein the first structure and the second structure are electrically disposed on the substrate.
8. The package structure module as claimed in claim 7, further comprising at least two conductive elements respectively connected between the first structure and one of the inputoutput pads and between the second structure and the other inputoutput pad.
9. The package structure module as claimed in claim 2, wherein the first structure has a plurality of pads formed on a top surface thereof and a plurality of first conductive traces, and the pads of the first structure correspond to the first open grooves and each first conductive trace is formed between each corresponding pad of the first structure and each corresponding first open groove; wherein the second structure has a plurality of pads formed on a top surface thereof and a plurality of second conductive traces, and the pads of the second structure correspond to the second open grooves and each second conductive trace is formed between each corresponding pad of the second structure and each corresponding second open groove.
10. The package structure module as claimed in claim 9, wherein each conductive structure is divided into three portions that are a first portion, a second portion and a third portion, and the second portion is electrically connected between the first portion and the third portion; wherein the first portion is formed on the corresponding pad of the first structure and the corresponding first conductive trace, the second portion traverses the corresponding first open groove and the corresponding second open groove in sequence and is formed on a lateral wall of the corresponding second open groove, and the third portion is formed on the corresponding second conductive trace in order to electrically connect with the corresponding pad of the second structure.
11. The package structure module as claimed in claim 9, wherein the second structure has an insulation layer formed on a top surface thereof in order to expose the pads and external sides of the second conductive traces.
12. The package structure module as claimed in claim 11, wherein each conductive structure is divided into a first portion and a second portion electrically connected to each other, the first portion is formed on the corresponding pad of the first structure and the corresponding first conductive trace, and the second portion traverses the corresponding first open groove and the corresponding second open groove in sequence and is formed on a lateral wall of the corresponding second open groove and the external side of the corresponding second conductive trace due to the obstruction of the insulation layer.
13. A method for packaging a package structure module with high density electrical connections, comprising:
providing a first structure and a second structure having a height higher than that of the first structure, wherein the first structure has a plurality of conductive materials formed on a top surface thereof, and the second structure has a plurality of second open grooves formed on a lateral wall thereof and close to the first structure;
electrically disposing the first structure and the second structure on a substrate;
slanting the substrate by a predetermined angle during a reflow process in order to make the conductive materials change into liquid conductive materials and make the liquid conductive materials traverse the second open grooves to flow to the second structure; and
cooling the liquid conductive materials to form a plurality of conductive structures electrically connected between the first structure and the second structure.
14. The method as claimed in claim 13, wherein the first structure has a plurality of first open grooves formed on a lateral wall thereof and respectively facing the second open grooves, and the liquid conductive materials respectively traverse the first open grooves.
15. The method as claimed in claim 13, wherein each second open groove has a depth of between 50 \u03bcm and 100 \u03bcm.
16. The method as claimed in claim 14, wherein each first open groove has a depth of between 50 \u03bcm and 100 \u03bcm.
17. The method as claimed in claim 14, wherein the first and the second open grooves are formed via etching.
18. The method as claimed in claim 13, wherein the first structure is a drive IC structure, and the second structure is an LED array structure.
19. The method as claimed in claim 13, wherein the substrate has at least two inputoutput pads, and at least two conductive elements are respectively connected between the first structure and one of the inputoutput pads and between the second structure and the other inputoutput pad.
20. The method as claimed in claim 14, wherein the first structure has a plurality of pads formed on a top surface thereof and a plurality of first conductive traces, and the pads of the first structure correspond to the first open grooves and each first conductive trace is formed between each corresponding pad of the first structure and each corresponding first open groove; wherein the second structure has a plurality of pads formed on a top surface thereof and a plurality of second conductive traces, and the pads of the second structure correspond to the second open grooves and each second conductive trace is formed between each corresponding pad of the second structure and each corresponding second open groove.
21. The method as claimed in claim 20, wherein each conductive structure is electrically connected between the corresponding pad of the first structure and the corresponding pad of the second structure.
22. The method as claimed in claim 20, wherein each conductive structure is divided into three portions that are a first portion, a second portion and a third portion, and the second portion is electrically connected between the first portion and the third portion; wherein the first portion is formed on the corresponding pad of the first structure and the corresponding first conductive trace, the second portion traverses the corresponding first open groove and the corresponding second open groove in sequence and is formed on a lateral wall of the corresponding second open groove, and the third portion is formed on the corresponding second conductive trace in order to electrically connect with the corresponding pad of the second structure.
23. The method as claimed in claim 20, wherein the second structure has an insulation layer formed on a top surface thereof in order to expose the pads and external sides of the second conductive traces.
24. The method as claimed in claim 23, wherein each conductive structure is divided into a first portion and a second portion electrically connected to each other, the first portion is formed on the corresponding pad of the first structure and the corresponding first conductive trace, and the second portion traverses the corresponding first open groove and the corresponding second open groove in sequence and is formed on a lateral wall of the corresponding second open groove and the external side of the corresponding second conductive trace due to the obstruction of the insulation layer.