1. A voltage selection circuit, comprising:
cross-coupled circuitry, wherein the cross-coupled circuitry comprises a first positive-channel field effect transistor (PFET) and a second PFET, wherein:
a source of the first PFET is coupled to a first voltage,
a gate of the first PFET is coupled to a second voltage,
a drain of the first PFET is coupled to an input of a header circuitry,
wherein the header device precharges a bit line of a memory cell,
a source of the second PFET is coupled to the second voltage,
a gate of the second PFET is coupled to the first voltage, and
a drain of the second PFET is coupled to the input to the header circuitry; and
diode circuitry, wherein the diode circuitry comprises a third PFET and a fourth PFET, wherein:
a source of the third PFET is coupled to the first voltage,
a gate of the third PFET is coupled to the input to the header circuitry,
a drain of the third PFET is coupled to the input to the header circuitry,
a source of the fourth PFET is coupled to the second voltage,
a gate of the fourth PFET is coupled to the input to the header circuitry, and
a drain of the fourth PFET is coupled to the input to the header circuitry.
2. The voltage selection circuit of claim 1, wherein, responsive to the first voltage being greater than the second voltage by a voltage threshold, the first voltage is applied to the header circuitry in order to precharge the bit line of the memory cell.
3. The voltage selection circuit of claim 2, wherein, responsive to the first voltage being greater than the second voltage by the voltage threshold, the first voltage deactivates the second NTT thereby preventing the second voltage from passing to the header circuitry.
4. The voltage selection circuit of claim 1, wherein, responsive to the second voltage being greater than the first voltage by a voltage threshold, the second voltage is applied to the header circuitry in order to precharge the bit line of the memory cell.
5. The voltage selection circuit of claim 4, wherein, responsive to the second voltage being greater than the first voltage by the voltage threshold, the second voltage deactivates the first PFET thereby preventing the first voltage from passing to the header circuitry.
6. The voltage selection circuit of claim 1, wherein, responsive to the first voltage being greater than the second voltage by less than a voltage threshold, the first voltage is applied to the header circuitry in order to precharge the bit line of the memory cell.
7. The voltage selection circuit of claim 6, wherein, responsive to the first voltage being greater than the second voltage by less than the voltage threshold, the first voltage is passed through the third PFET to the header circuitry.
8. The voltage selection circuit of claim 1, wherein, responsive to the second voltage being greater than the first voltage by less than a voltage threshold, the second voltage is applied to the header circuitry in order to precharge the bit line of the memory cell.
9. The voltage selection circuit of claim 8, wherein, responsive to the second voltage being greater than the first voltage by less than the voltage threshold, the second voltage is passed through the fourth PFET to the header circuitry.
10. The voltage selection circuit of claim 1, wherein, responsive to an absolute difference of the first voltage and the second voltage being less than a voltage threshold, both the third PFET and the fourth PFET behave like a diode in analog mode thereby allowing a maximum of the first voltage or the second voltage to be driven down to Vmax minus the voltage threshold.
11. A memory comprising:
a set of memory cells;
a voltage selection circuit coupled to the set of memory cells, wherein the voltage selection circuit comprises:
cross-coupled circuitry, wherein the cross-coupled circuitry comprises a first positive-channel field effect transistor (PFET) and a second PFET, wherein:
a source of the first PFET is coupled to a first voltage,
a gate of the first PFET is coupled to a second voltage,
a drain of the first PFET is coupled to an input of a header circuitry,
wherein the header device precharges a bit line of the set of memory cells,
a source of the second PFET is coupled to the second voltage,
a gate of the second PFET is coupled to the first voltage, and
a drain of the second PFET is coupled to the input to the header circuitry; and
diode circuitry, wherein the diode circuitry comprises a third PFET and a fourth PFET, wherein:
a source of the third PFET is coupled to the first voltage,
a gate of the third PFET is coupled to the input to the header circuitry,
a drain of the third PFET is coupled to the input to the header circuitry,
a source of the fourth PFET is coupled to the second voltage,
a gate of the fourth PFET is coupled to the input to the header circuitry, and
a drain of the fourth PFET is coupled to the input to the header circuitry.
12. The memory of claim 11, wherein, responsive to the first voltage being greater than the second voltage by a voltage threshold, the first voltage is applied to the header circuitry in order to precharge the bit line of the memory cell.
13. The memory of claim 12, wherein, responsive to the first voltage being greater than the second voltage by the voltage threshold, the first voltage deactivates the second PFET thereby preventing the second voltage from passing to the header circuitry.
14. The memory of claim 11, wherein, responsive to the second voltage being greater than the first voltage by a voltage threshold, the second voltage is applied to the header circuitry in order to precharge the bit line of the memory cell.
15. The memory of claim 14, wherein, responsive to the second voltage being greater than the first voltage by the voltage threshold, the second voltage deactivates the first PFET thereby preventing the first voltage from passing to the header circuitry.
16. The memory of claim 11, wherein, responsive to the first voltage being greater than the second voltage by less than a voltage threshold, the first voltage is applied to the header circuitry in order to precharge the bit line of the memory cell and wherein, responsive to the first voltage being greater than the second voltage by less than the voltage threshold, the first voltage is passed through the third PFET to the header circuitry.
17. The memory of claim 11, wherein, responsive to the second voltage being greater than the first voltage by less than a voltage threshold, the second voltage is applied to the header circuitry in order to precharge the bit line of the memory cell and wherein, responsive to the second voltage being greater than the first voltage by less than the voltage threshold, the second voltage is passed through the fourth PFET to the header circuitry.
18. The memory of claim 11, wherein, responsive to an absolute difference of the first voltage and the second voltage being less than a voltage threshold, both the third PFET and the fourth PFET behave like a diode in analog mode thereby allowing a maximum of the first voltage or the second voltage to be driven down to Vmax minus the voltage threshold.
19. An apparatus, comprising:
a processor; and
a memory coupled to the processor, wherein the memory comprises:
a set of memory cells;
a voltage selection circuit coupled to the set of memory cells, wherein the voltage selection circuit comprises:
cross-coupled circuitry, wherein the cross-coupled circuitry comprises a first positive-channel field effect transistor (PFET) and a second PFET, wherein:
a source of the first PFET is coupled to a first voltage,
a gate of the first PFET is coupled to a second voltage,
a drain of the first PFET is coupled to an input of a header circuitry, wherein the header device precharges a bit line of a memory cell,
a source of the second PFET is coupled to the second voltage,
a gate of the second PFET is coupled to the first voltage, and
a drain of the second PFET is coupled to the input to the header circuitry; and
diode circuitry, wherein the diode circuitry comprises a third PFET and a fourth PFET, wherein:
a source of the third PFET is coupled to the first voltage,
a gate of the third PFET is coupled to the input to the header circuitry,
a drain of the third PFET is coupled to the input to the header circuitry,
a source of the fourth PFET is coupled to the second voltage,
a gate of the fourth PFET is coupled to the input to the header circuitry, and
a drain of the fourth PFET is coupled to the input to the header circuitry.
20. The apparatus of claim 19, wherein, responsive to the first voltage being greater than the second voltage by a voltage threshold, the first voltage is applied to the header circuitry in order to precharge the bit line of the memory cell and wherein, responsive to the first voltage being greater than the second voltage by the voltage threshold, the first voltage deactivates the second PFET thereby preventing the second voltage from passing to the header circuitry.
21. The apparatus of claim 19, wherein, responsive to the second voltage being greater than the first voltage by a voltage threshold, the second voltage is applied to the header circuitry in order to precharge the bit line of the memory cell and wherein, responsive to the second voltage being greater than the first voltage by the voltage threshold, the second voltage deactivates the first PFET thereby preventing the first voltage from passing to the header circuitry.
22. The apparatus of claim 19, wherein, responsive to the first voltage being greater than the second voltage by less than a voltage threshold, the first voltage is applied to the header circuitry in order to precharge the bit line of the memory cell and wherein, responsive to the first voltage being greater than the second voltage by less than the voltage threshold, the first voltage is passed through the third PFET to the header circuitry.
23. The apparatus of claim 19, wherein, responsive to the second voltage being greater than the first voltage by less than a voltage threshold, the second voltage is applied to the header circuitry in order to precharge the bit line of the memory cell and wherein, responsive to the second voltage being greater than the first voltage by less than the voltage threshold, the second voltage is passed through the fourth PFET to the header circuitry.
24. The apparatus of claim 19, wherein, responsive to an absolute difference of the first voltage and the second voltage being less than a voltage threshold, both the third PFET and the fourth PFET behave like a diode in analog mode thereby allowing a maximum of the first voltage or the second voltage to be driven down to Vmax minus the voltage threshold.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An outboard motor fuel controller for controlling an amount of fuel fed to an engine of an outboard motor mounted on a boat, the outboard motor fuel controller comprising:
a deceleration determining section arranged to determine deceleration of the boat;
an engine speed detecting section arranged to detect engine speed;
an engine load detecting section arranged to detect a load on the engine; and
a controller arranged to control the amount of fuel fed to the engine when the boat is in deceleration according to the detected engine speed and engine load; wherein
the deceleration determining section determines that the boat is in deceleration when a) a throttle request value is equal to or less than a predetermined deceleration determining throttle value, b) the engine speed is greater than a predetermined deceleration determining revolution, and c) a predetermined deceleration time limit elapses and conditions a) and b) are still satisfied.
2. The outboard motor fuel controller of claim 1, wherein the controller, when starting control of the fuel amount fed to the engine, is arranged to preset an initial value of a fuel compensation amount according to the engine speed and the engine load.
3. An outboard motor fuel controller for controlling an amount of fuel fed to an engine of an outboard motor mounted on a boat, the outboard motor fuel controller comprising:
a deceleration determining section arranged to determine deceleration of the boat;
an engine speed detecting section arranged to detect engine speed;
an engine load detecting section arranged to detect a load on the engine; and
a controller arranged to control the amount of fuel fed to the engine when the boat is in deceleration according to the detected engine speed and engine load; wherein
the controller, when starting control of the fuel amount fed to the engine, is arranged to preset an initial value of a fuel compensation amount according to the engine speed and the engine load; and
the controller carries out a dividing calculation of the preset initial value of the fuel compensation amount at certain time intervals to obtain an estimated value of the fuel compensation amount.
4. The outboard motor fuel controller of claim 3, wherein the controller determines a compensation factor based on the calculated, estimated value of the fuel control compensation amount and on the engine speed, and determines a final fuel feed amount based on the compensation factor.