1. A method for manufacturing a semiconductor device using a salicide process, comprising:
forming a gate dielectric layer over a silicon substrate, said substrate defining a PMOS region and an NMOS region;
forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region, over the gate dielectric layer, the first and silicon patterns each defining side walls and a top surface;
forming a first mask pattern that covers the PMOS region and exposes the NMOS region;
doping n-type impurities into the first silicon pattern in the exposed NMOS region and an exposed first portion of the silicon substrate that is adjacent to the first silicon pattern;
forming a first metal layer that covers the side walls and the top surface of the first silicon pattern and the exposed first portion of the silicon substrate;
forming a doped first gate and a first junction by performing a first heat treatment to silicify the first silicon pattern and the exposed first portion of the silicon substrate;
forming a second mask pattern that covers the NMOS region and exposes the PMOS region;
doping p-type impurities into the second silicon pattern in the exposed PMOS region and an exposed second portion of the silicon substrate that is adjacent to the second silicon pattern;
forming a second metal layer that covers the side walls and the top surface of the second silicon pattern and the exposed second portion of the silicon substrate; and
forming a doped second gate and a second junction by performing a second heat treatment to completely silicify the second silicon pattern and the exposed second portion of the silicon substrate.
2. The method of claim 1, wherein the gate dielectric layer comprises a material having a high dielectric constant higher than the dielectric constant of silicon oxide.
3. The method of claim 1, comprising forming the first and second silicon patterns by:
depositing a silicon layer over the gate dielectric layer;
forming a partition pattern over the silicon layer, said partition pattern defining side walls;
attaching spacers to side walls of the partition pattern;
selectively removing the partition pattern to expose a portion of the silicon layer; and
forming the first and second silicon patterns by selectively removing the portion of the silicon layer exposed by the spacers.
4. The method of claim 3, comprising forming the silicon layer by depositing a polysilicon layer.
5. The method of claim 3, comprising forming the silicon layer by:
depositing a polysilicon layer as a seed over the gate dielectric layer;
and epitaxially growing silicon over the polysilicon layer.
6. The method of claim 3, comprising forming the partition pattern using a silicon oxide (SiO2) based material, and forming the spacer layer using a silicon nitride (Si3N4) layer or a nitride compound.
7. The method of claim 1, wherein the doped first gate has a work function different from that of the doped second gate.
8. The method of claim 1, comprising forming the first and second metal layers using an identical metal material or a metal nitride compound in each case.
9. The method of claim 8, comprising forming the first and second metal layers are formed including cobalt (Co), nickel (Ni), a cobalt nitride compound or a nickel nitride compound.
10. The method of claim 1, comprising forming the first and second metal layers using a different metal material or metal nitride compound in each case.
11. The method of claim 10, comprising forming at least one of the first and second metal layers from a metal or metal nitride compound selected from the group consisting of cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), copper (Cu), molybdenum (Mo), tantalum (Ta), zirconium (Zr), platinum (Pt), and nitride compounds thereof.
12. The method of claim 1, wherein the first or second mask pattern comprises a silicon nitride layer or a silicon oxide layer.
13. A method for manufacturing a semiconductor device using a salicide process, comprising:
forming a gate dielectric layer over a silicon substrate defining a PMOS region and an NMOS region;
forming a silicon layer over the dielectric layer;
forming a partition pattern over the silicon layer, said partition pattern defining side walls;
attaching spacers to side walls of the partition patterns;
selectively removing the partition pattern to expose a portion of the silicon layer;
forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region by selectively removing the portion of the silicon layer exposed by the spacers, the first and silicon patterns each defining side walls and a top surface;
forming a first mask pattern that covers the PMOS region and exposes the NMOS region;
doping n-type impurities into the first silicon pattern in the exposed NMOS region and a first exposed portion of the silicon substrate that is adjacent to the first silicon pattern;
forming a first metal layer that covers the side walls and the top surface of the first silicon pattern and the exposed first portion of the silicon substrate;
forming a first gate and a first junction by performing a first heat treatment to completely silicify the first silicon pattern and the exposed first portion of the silicon substrate;
forming a second mask pattern that covers the NMOS region and exposes the PMOS region;
doping p-type impurities into the second silicon pattern in the exposed PMOS region and an exposed second portion of the silicon substrate that is adjacent to the second silicon pattern;
forming a second metal layer that covers the side walls and the top surface of the second silicon pattern and the exposed second portion of the silicon substrate; and
forming a second gate and a second junction by performing a second heat treatment to completely silicify the second silicon pattern and the exposed second portion of the silicon substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A poppet valve, comprising:
a valve body, said valve body having a central axis, a flow inlet, and a flow outlet;
a poppet guide disposed inside the valve body so as to form a first portion of a flow passage from the flow inlet to the flow outlet, said flow passage being formed between an inside surface of the valve body and an outside surface of the poppet guide and passing through at least one hole in the poppet guide;
a poppet shutter disposed inside the poppet guide so as to form a second portion of the flow passage between an outside surface of the poppet shutter and the inside surface of the valve body; and
a biasing member disposed inside an inner chamber of the poppet guide, said biasing member being configured to bias the poppet shutter toward an inside surface of the flow inlet so as to block the flow passage, wherein said poppet guide further includes at least one discharge hole placing the inner chamber of the poppet guide in flow communication with a region of low static pressure of the flow passage.
2. The poppet valve according to claim 1, wherein the at least one discharge hole connects to the flow passage at the at least one hole.
3. The poppet valve according to claim 1, wherein the region of low static pressure is a region of flow acceleration.
4. The poppet valve according to claim 3, wherein the amount of flow acceleration is controlled by a diameter of the at least one hole in the poppet guide.
5. The poppet valve according to claim 1, wherein the at least one discharge hole is inclined with respect to the central axis of the valve body.
6. The poppet valve according to claim 5, wherein an inclination angle of the at least one discharge hole varies between 10 and 25 degrees.
7. The poppet valve according to claim 6, wherein the inclination angle is approximately 19 degrees.
8. The poppet valve according to claim 1, wherein the at least one discharge hole is disposed in the poppet guide so as to reduce a pressure force acting against an inner surface of the poppet shutter toward the valve inlet.
9. The poppet valve according to claim 1, wherein said biasing member is a spring.
10. A hyper compressor comprising a poppet valve according to claim 1.
11. A method for reducing a closing pressure force acting on a poppet shutter of a poppet valve, said poppet valve having a valve body with a central axis, a flow inlet, and a flow outlet, said poppet valve including further a poppet guide and a biasing member configured to bias the poppet shutter disposed inside the poppet guide against the valve body so as to close the poppet valve, the method comprising:
accelerating the flow in a flow passage of the valve so as to reduce the static pressure in a region of the flow passage, said flow passage being disposed so as to place said flow inlet in flow communication with said flow outlet, a portion of said flow passage being formed between the poppet guide and the valve body; and
placing an inner chamber of the poppet guide in flow communication with the region of reduced static pressure of the flow passage so as to reduce a fluid pressure force acting on an inner surface of the poppet shutter toward an inner surface of the valve body to cause the poppet valve to close.
12. The method according to claim 11, wherein said accelerating the flow further comprises accelerating the flow through at least one hole in the poppet guide and said region of low static pressure is located in a portion of the flow passage where said at least one hole is located.
13. The method according to claim 11, wherein said placing in flow communication comprises placing the inner chamber of the poppet guide in flow communication with the region of the flow passage with the reduced static pressure via at least one discharge hole disposed in the poppet guide.
14. The method according to claim 13, wherein the at least one discharge hole is inclined with respect to the central axis of the valve body.
15. The method according to claim 14, wherein an inclination angle of the at least one discharge hole varies between 10 and 25 degrees.
16. The method according to claim 15, wherein the inclination angle is approximately 19 degrees.
17. A poppet valve, comprising:
a valve body, said valve body having a central axis, a flow inlet, and a flow outlet;
a poppet guide disposed inside the valve body so as to form a first portion of a flow passage from the flow inlet to the flow outlet, said flow passage being formed between an inside surface of the valve body and an outside surface of the poppet guide and passing through at least one hole in the poppet guide;
a poppet shutter disposed inside the poppet guide so as to form a second portion of the flow passage between an outside surface of the poppet shutter and the inside surface of the valve body;
a spring disposed inside an inner chamber of the poppet guide, said spring being configured to bias the poppet shutter toward an inside surface of the flow inlet so as to block the flow passage; and
a purge flow passage placing the inner chamber of the poppet guide in flow communication with a region of low static pressure of the first portion of the flow passage at the location of the at least one hole, said purge flow passage being sloped with respect to the central axis of the valve body.
18. The poppet valve according the claim 17, wherein a ratio of a diameter of the at least one hole to a diameter of the flow inlet ranges from about 0.36 to about 0.44.
19. The poppet valve according to claim 17, wherein an inclination angle of the at least one discharge hole varies from approximately 10 to approximately 25 degrees.
20. A hyper compressor comprising a poppet valve according to claim 17.