1. A light-emitting diode device having two electrode pads for connecting to an external power, comprising:
a substrate;
a plurality of light-emitting diode units on the substrate; and
a plurality of conductive connecting structures electrically connecting the plurality of light-emitting diode units;
wherein the two electrode pads are encircled by the plurality of light-emitting diode units.
2. The light-emitting diode device of claim 1, wherein each of the plurality of light-emitting diode units comprises a first conductive type semiconductor layer on the substrate; a second conductive type semiconductor layer on the first conductive type semiconductor layer; and a light-emitting layer arranged between the first conductive type semiconductor layer and the second conductive type semiconductor layer.
3. The light-emitting diode device of claim 2, wherein each of the light-emitting diode units further comprises a first electrode formed on the first conductive type semiconductor layer and a second electrode formed on the second conductive type semiconductor layer.
4. The light-emitting diode device of claim 1, wherein the plurality of light-emitting diode units are spaced apart from each other with a distance larger than 35 \u03bcm.
5. The light-emitting diode device of claim 1, further comprising an adhesive layer formed between the substrate and the plurality of light-emitting diode units
6. The light-emitting diode device of claim 5, wherein the adhesive layer is a transparent adhesive layer.
7. The light-emitting diode device of claim 6, wherein the material of the transparent adhesive layer comprises a polymer material.
8. The light-emitting diode device of claim 6, wherein the material of the transparent adhesive layer comprises metal oxide.
9. The light-emitting diode device of claim 6, wherein the material of the transparent adhesive layer comprises inorganic material.
10. The light-emitting diode device of claim 1, wherein the substrate is a transparent substrate.
11. The light-emitting diode device of claim 1, wherein the substrate is a multi-layered substrate.
12. The light-emitting diode device of claim 2, wherein each of the conductive connecting structures is arranged between two adjacent light-emitting diode units and electrically connect the first conductive type semiconductor layer of one of two adjacent light-emitting diode units to the second conductive type semiconductor layer of the other of the two adjacent light-emitting diode units.
13. The light-emitting diode device of claim 1, wherein one of the plurality of light-emitting diode units is spaced apart from an edge of the substrate with a shortest distance not smaller than 20 \u03bcm.
14. The light-emitting diode device of claim 1, wherein the substrate comprises a first side and a second side, a total number of the plurality of light-emitting diode units formed along the first side is equal to a total number of the plurality of light-emitting diode units formed along the second side.
15. The light-emitting diode device of claim 1, further comprising one light-emitting diode unit encircled by the plurality of light-emitting diode units.
16. The light-emitting diode device of claim 1, wherein the plurality of light-emitting diode units is substantially arranged in a lattice form.
17. The light-emitting diode device of claim 12, wherein each of the plurality of light-emitting diode units comprises a longer side and a shorter side, and one of the conductive connecting structures is arranged between the shorter sides of the two adjacent light-emitting diode units.
18. The light-emitting diode device of claim 17, wherein the longer side of one of the plurality of light-emitting diode units is perpendicular to the longer side of another one of the plurality of light-emitting diode units.
19. The light-emitting diode device of claim 12, further comprising an insulating layer partially formed on the plurality of light-emitting diode units and between two adjacent light-emitting diode units.
20. The light-emitting diode device of claim 1, each of the plurality of light-emitting diode units comprises a growth substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A clock generator comprising:
a resistor;
a MOSFET having a gate, a drain and a source connected to said resistor for generating a reference current;
a first reference voltage independent on VDD and temperature for controlling said MOSFET;
a current mirror circuit for generating a first and a second mirror current by mirroring said reference current;
a first capacitor receiving said first mirror current and generating a first charged voltage;
a second capacitor receiving said second mirror current and generating a second charged voltage;
a second reference voltage generated from an input supply voltage for controlling said first and second charged voltage; and
a logic circuit receiving said first and second charged voltage and generating a clock signal.
2. The clock generator as set forth in claim 1, wherein said first capacitor, second capacitor and resistor determine the period of said clock signal.
3. A clock generator comprising:
a current mirror circuit for generating a first and a second mirror current by mirroring a reference current, which increases with temperature; and
a first capacitor receiving the first mirror current and generating a first charged voltage;
a second capacitor receiving the second mirror current and generating a second charged voltage; and
a logic circuit receiving the first and second charged voltages and generating a clock signal.
4. The clock generator as set forth in claim 3, and further comprising;
a resistor; and
a MOSFET having a gate, a drain and a source, the MOSFET being connected to the resistor for generating the reference current.
5. The clock generator as set forth in claim 4, wherein the MOSFET has a threshold voltage (Vt) that decreases with increasing temperature.
6. The clock generator as set forth in claim 5, wherein the threshold voltage (Vt) decreases with increasing temperature so that a current through the MOSFET increases with increasing temperature.
7. The clock generator as set forth in claim 6, wherein the threshold voltage (Vt) decreases with increasing temperature so that a frequency of the clock signal increases with increasing temperature.
8. The clock generator as set forth in claim 4, wherein the first capacitor, second capacitor and resistor determine the period of the clock signal.
9. The clock generator as set forth in claim 4, and further comprising a first reference voltage independent on VDD and temperature for controlling the MOSFET.
10. The clock generator as set forth in claim 7, and further comprising a second reference voltage generated from an input supply voltage for controlling the first and second charged voltage.
11. A method of generating a clock signal in a charge pump, comprising:
mirroring a reference current, which increases with temperature, to generate a first and a second mirror current;
receiving the first mirror current and generating a first charged voltage with a first capacitor;
receiving the second mirror current and generating a second charged voltage with a second capacitor; and
receiving the first and second charged voltages into a logic circuit and generating a clock signal.
12. The method as set forth in claim 11, wherein the mirroring of a reference current is preceded by generating the reference current using a MOSFET connected to a resistor, wherein a threshold voltage (Vt) of the MOSFET decreases with increasing temperature.
13. The method as set forth in claim 12, wherein the threshold voltage (Vt) decreases with increasing temperature so that a current through the MOSFET increases with increasing temperature.
14. The method as set forth in claim 13, wherein the threshold voltage (Vt) decreases with increasing temperature so that a frequency of the clock signal increases with increasing temperature.
15. The method as set forth in claim 12, and further comprising controlling the MOSFET with a first reference voltage independent of a supply voltage VDD and temperature.