1. An apparatus comprising control circuitry configured to write a logic state to a resistive sense element (RSE) while simultaneously verifying the written logic state of the RSE, a first sense amplifier coupled to the RSE which is used during said simultaneous verification, and a second sense amplifier coupled to the RSE which is used to read the written logic state of the RSE during a subsequent read operation.
2. The apparatus of claim 1, wherein the logic state of the RSE is written by an application of a write current to the RSE, and wherein the written logic state is simultaneously verified by sensing a voltage drop across the RSE during the application of the write current.
3. The apparatus of claim 1, wherein the RSE is marked as defective after an error is detected during said simultaneous verification.
4. The apparatus of claim 1, wherein a first reference voltage is supplied to the first sense amplifier and a different, second reference voltage is supplied to the second sense amplifier.
5. The apparatus of claim 1, wherein the first sense amplifier receives as an input a voltage drop across the RSE, said voltage drop generated during passage of a write current through the RSE to write the logical state.
6. The apparatus of claim 5, wherein the first sense amplifier compares the voltage drop to a first reference voltage responsive to a first value for the written logical state, and wherein the first sense amplifier compares the voltage drop to a second reference voltage responsive to a second value for the written logical state.
7. The apparatus of claim 1, wherein the writing of the RSE and verification of the logic state uses a single write current pulse.
8. The apparatus of claim 1, wherein the writing of the RSE and verification of the logic state occurs over a single write clock cycle.
9. The apparatus of claim 1, wherein the RSE is characterized as a magnetic tunneling junction (MTJ).
10. A method comprising:
writing a logical state to a resistive sense element (RSE) by applying a write current to the RSE to write the logical state thereto, the applied write current generating a voltage drop across the RSE; and
simultaneously verifying the written logical state of the RSE during the writing step by sensing said voltage drop.
11. The method of claim 10, wherein the RSE is marked as defective after an error is detected.
12. The method of claim 10, wherein the RSE is connected to a plurality of sense amplifiers.
13. The method of claim 12, wherein a multiplexer provides reference values to each sense amplifier.
14. The method of claim 13, wherein the reference values are respectively used for a write operation and a read operation.
15. The method of claim 10, wherein the simultaneously verifying step comprises using a sense amplifier to compare the voltage drop to a reference voltage.
16. A memory, comprising:
an array of memory cells each comprising a resistive sense element (RSE);
a write circuit adapted to apply a write current to a selected memory cell of the array to write a logical state to the associated RSE of said cell, the write current generating a voltage drop across the cell; and
a sense amplifier adapted to simultaneously verify the written logic state by comparing the voltage drop to a reference voltage.
17. The memory of claim 16, in which the sense amplifier outputs a data signal in response to the voltage drop and the reference voltage, the data signal having a value indicative of the written logic state of the RSE.
18. The memory of claim 17, in which the reference voltage has a magnitude selected in relation to the written logic state so that a first reference voltage is used for a first written logic state and a different, second reference voltage is used for a different, second written logic state.
19. The memory of claim 18, further comprising a multiplexor circuit which respectively presents the first and second reference voltages to the sense amplifier responsive to an input signal indicative of said logic state.
20. The memory of claim 16, in which the sense amplifier is characterized as a first sense amplifier, the storage device further comprising a second sense amplifier coupled to the RSE which is used to subsequently verify the written logic state of the RSE responsive to an application of a read current through the selected memory cell during a subsequent read operation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A prediction image generation method for generating a prediction image from encoded data obtained by subjecting a video image to prediction encoding, the video image comprising a luminance component and first and second color difference components, the method comprising:
receiving an input of encoded data obtained by encoding, for one or more to-be-decoded blocks, a plurality of combinations, each combination comprising (A) a first weighting factor for the luminance component, (B) a second weighting factor for the first color difference component, (C) a third weighting factor for the second color difference component, (D) a first offset for the luminance component, (E) a second offset for the first color difference component, and (F) a third offset for the second color difference component, and encoding, for a to-be-decoded block, a given number of indices, each index indicating one combination of the plurality of combinations and a reference image, respectively;
deriving, for a to-be-decoded block, a given number of the plurality of combinations of the weighting factors and the offsets from the given number of indices and the plurality of combinations; and
generating a prediction image by multiplying the luminance and first and second color difference components of a given number of reference images by the weighting factors corresponding to the respective reference images and adding the offsets, respectively, to results of the multiplying.