1. A process of reducing the cholesterol content in cholesterol-containing organic oils or fats, particularly animal oils or fats, the process comprising the steps of:
adding at least one of demineralized water and distilled water having a set pH-value to the cholesterol-containing oils or fats, thereby forming a mixture; and
separating the mixture into a cholesterol-containing aqueous phase and a cholesterol-reduced oil or fat phase.
2. The process according to claim 1, wherein the separating into the cholesterol-containing aqueous phase takes place in a centrifuge.
3. The process according to claim 1, wherein the separating into the cholesterol-containing aqueous phase takes place in a separating centrifuge.
4. The process according to claim 1, wherein the at least one of demineralized water and distilled water has a set pH-value between 4 and 6.
5. The process according to claim 1, wherein the at least one of demineralized water and distilled water has a set pH-value between 6.5 and 8.
6. The process according to claim 1, wherein the separating takes place within a time period of less than 5 to 10 minutes after the adding of the at least one of demineralized water and distilled water.
7. The process according to claim 1, wherein the steps of adding and separating repeated at least once.
8. The process according to claim 1, wherein the cholesterol-containing oils or fats includes cut-up beef drippings.
9. The process according to claim 1, wherein the at least one of demineralized water and distilled water is added to the cholesterol-containing oils or fats at a ratio of 1:1.
10. The process according to claim 1, wherein the separating into the cholesterol-containing aqueous phase takes place in a separator.
11. The process according to claim 10, wherein the separator includes a vertical axis of rotation and a disk stack.
12. The process according to claim 1, wherein the at least one of the demineralized water and distilled water has set pH-value between 5 and 6.
13. The process according to claim 1, wherein the separating takes place within a period of less than 120 seconds after the adding of the at least one of demineralized water and distilled water.
14. The process according to claim 1, wherein the separating takes place within a time period of less than 60 seconds after the adding of the at least one of demineralized water and distilled water.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A packaged semiconductor, comprising:
a leadframe comprising a plurality of leads and a paddle, each one of said plurality of leads having a top portion and a bottom portion;
a semiconductor chip attached to said paddle;
a plurality of wires electrically connecting said semiconductor chip to said plurality of leads; and
a sealing material encapsulating said leadframe, said semiconductor chip, and said plurality of wires, said sealing material forming a top surface and a bottom surface of said packaged semiconductor, said top portion of said plurality of leads protruding from said top surface of said packaged semiconductor and said bottom portion of said plurality of leads protruding from said bottom portion of said packaged semiconductor.
2. The semiconductor package of claim 1 wherein said plurality of leads are etched.
3. The semiconductor package of claim 1 wherein said paddle is etched.
4. The semiconductor package of claim 1 wherein said paddle has a bottom side resting flush against said bottom surface of said semiconductor package.
5. The semiconductor package of claim 1 wherein said top portion and said bottom portion of said plurality of leads are electroplated.
6. The semiconductor package of claim 1 wherein said plurality of electrically conductive wires are electroplated with a material selected from the group consisting of: silver, gold, aluminum, or an alloy thereof
7. The semiconductor package of claim 1 wherein said plurality of leads are arranged in at least one single line wherein said at least one single line surrounds said paddle.
8. A semiconductor package of claim 1 wherein said plurality of leads are randomly dispersed in a plurality of lines surrounding said paddle.
9. A packaged semiconductor, comprising:
a leadframe comprising a plurality of leads and a location for attaching a semiconductor chip, each one of said plurality of leads having a top portion and a bottom portion;
a semiconductor chip attached to said location for attaching a semiconductor chip;
a plurality of wires electrically connecting said semiconductor chip to said plurality of leads; and
a sealing material encapsulating said leadframe, said semiconductor chip, and said plurality of wires, said sealing material forming a top surface and a bottom surface of said packaged semiconductor, said top portion of said plurality of leads protruding from said top surface of said packaged semiconductor and said bottom portion of said plurality of leads protruding from said bottom portion of said packaged semiconductor.
10. The semiconductor package of claim 9 wherein said plurality of leads are etched.
11. The semiconductor package of claim 9 wherein said paddle has a bottom side resting flush against said bottom surface of said semiconductor package.
12 The semiconductor package of claim 9 wherein said paddle is etched.
13. The semiconductor package of claim 9 wherein said top portion and said bottom portion of said plurality of leads are electroplated.
14. The semiconductor package of claim 9 wherein said plurality of electrically conductive wires are selected from the group consisting of: silver, gold, aluminum, or an alloy thereof.
15. The semiconductor package of claim 9 wherein said plurality of leads are arranged in at least one single line wherein said at least one single line surrounds said paddle.
16. A semiconductor package of claim 9 wherein said plurality of leads are randomly dispersed in a plurality of lines surrounding said paddle.
17. A method for stacking semiconductor packages for semiconductor chips, said method for stacking semiconductor packages comprising the steps of:
physically and electrically connecting a first side of a first semiconductor package to a printed circuit board, said first semiconductor package having a first plurality of leads, each one of said first plurality of leads having a first section protruding out of a first top surface of said first semiconductor package and a second section protruding out of a first bottom surface of said first semiconductor package; and
physically and electrically connecting a second semiconductor package to a second side of said first semiconductor package, said second side located generally opposite of said first side, said second semiconductor package having a second plurality of leads in generally the same place as said first plurality of leads.
18. The method for stacking semiconductor packages as in claim 17 further comprising the step of soldering said first semiconductor package to said printed circuit board.
19. A method for stacking semiconductor packages as in claim 17 further comprising the step of soldering said second semiconductor package to said first semiconductor package.
20. A method for stacking semiconductor packages as in claim 17, further comprising sandwiching a solder ball between said first plurality of leads of said first semiconductor package and said second plurality of leads of said second semiconductor package prior to physically and electrically connecting said second semiconductor package to said first semiconductor package.
21. A method for stacking semiconductor packages as in claim 17 further comprising the step of soldering said first semiconductor package to said printed circuit board.
22. A method for stacking semiconductor packages as in claim 17 further comprising the step of soldering said second semiconductor package to said first semiconductor package.
23. A method for manufacturing a semiconductor package for a semiconductor chip, said method for manufacturing a semiconductor package comprising the steps of:
attaching a semiconductor chip to a paddle of a lead frame, said lead frame having a plurality of leads surrounding said paddle;
electrically connecting said semiconductor chip to at least some of said plurality of leads via a plurality of wires; and
applying a sealing material to secure said semiconductor chip, said lead frame, and said plurality of wires, said sealing material forming a top side and a bottom side of said semiconductor package, with a first section of each of said plurality of leads protruding out of said top side of said semiconductor package and a second section of each of said plurality of leads protruding out of said bottom side of said semiconductor package.
24. A semiconductor package, comprising:
a lead frame having a plurality of leads and a paddle for supporting a semiconductor chip, each one of said plurality of leads having a top portion protruding from a top surface of said semiconductor package and a bottom portion protruding from a bottom surface of said semiconductor package;
a plurality of wires electrically connecting said semiconductor chip to said plurality of leads; and
sealing material encapsulating said lead frame, said semiconductor chip, and said plurality of wires.
25. A lead frame, comprising:
a paddle for supporting a semiconductor chip; and
a plurality of leads, each one of said plurality of leads having an attachment point for a plurality of wires to electrically connect said semiconductor chip to at least some of said plurality of leads, each one of said plurality of leads configured to be encapsulated such that a top portion of each one of said plurality of leads protrudes from a top surface of an encapsulant and a bottom portion of each one of said plurality of leads protrudes from a bottom surface of said encapsulant.