1. A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element, each of the at least one NV memory element comprising a plurality of blocks, the method applied to a controller of the memory apparatus, the controller being used to control the at least one NV element, the method comprising following steps:
temporarily storing data received from a host device into a volatile memory in the controller and utilizing the data in the volatile memory as received data, and dynamically monitoring a data amount of the received data to determine whether to immediately write the received data into the at least one NV memory element, wherein at least one write command received from the host device indicates that the host device requests to write the data; and
when determining to immediately write the received data into the at least one NV memory element, directly writing the received data into a specific block configured to be a Multiple Level Cell (MLC) memory block within a specific NV memory element of the at least one NV memory element, rather than indirectly writing the received data into the specific block by first temporarily writing the received data into any other block configured to be a Single Level Cell (SLC) memory block.
2. The method of claim 1, wherein under a situation that a memory cell in the specific block is used to store a plurality of bits, the plurality of bits need to be repeatedly written into the memory cell for a predetermined number of times, so that the memory cell is correctly programmed in the specific NV memory element, thus making each of the plurality of bits correctly stored into the memory cell for further reading; and the predetermined number of times is larger than 1.
3. The method of claim 2, wherein the step of dynamically monitoring the data amount of the received data comprises:
when the data amount of the received data reaches a predetermined data amount threshold, determining to immediately write the received data into the at least one NV memory element;
wherein a storage capacity of the volatile memory is larger than or equal to a product of the predetermined data amount threshold and the predetermined number of times, to allow at least a portion of the received data to be used in a repeated write operation of the memory cell.
4. The method of claim 3, wherein the predetermined data amount threshold is equal to a storage capacity of a set of memory cells belonging to a word-line in the specific NV memory element.
5. The method of claim 4, wherein any of the plurality of blocks comprises a predetermined number of pages; and the method further comprises:
receiving a plurality of sets of data from the host device, respectively, and temporarily storing the plurality of sets of data into the volatile memory, wherein each of the plurality of sets of data comprises a plurality of pages, and a data amount of each of the plurality of sets of data is equal to the predetermined data amount threshold; and
reading the plurality of sets of data from the volatile memory, to directly write the plurality of sets of data into the specific block, respectively, and directly writing a first set of data of the plurality of sets of data into the specific block several times, wherein a number of times the first set of data is written into the specific block reaches the predetermined number of times, so that a specific set of memory cells belonging to a specific word-line in the specific block is correctly programmed in the specific NV memory element, thus making each bit of the first set of data correctly stored in the specific set of memory cells for further reading.
6. The method of claim 2, wherein any of the plurality of blocks comprises a predetermined number of pages; and the method further comprises:
respectively receiving a first set of data comprising a plurality of pages from the host device in a page-by-page manner until a total received data amount of the first set of data reaches a predetermined data amount threshold, and temporally storing the first set of data into the volatile memory, wherein before the total received data amount of the first set of data reaches the predetermined data amount threshold, the first set of data is not written into the specific block; and
when the total received data amount of the first set of data reaches the predetermined data amount threshold, reading at least a portion of the first set of data from the volatile memory to directly write the first set of data into the specific block.
7. The method of claim 6, further comprising:
respectively receiving a second set of data comprising a plurality of pages from the host device in a page-by-page manner until a total received data amount of the second set of data reaches the predetermined data amount threshold, and temporally storing the second set of data into the volatile memory, wherein before the total received data amount of the second set of data reaches the predetermined data amount threshold, the second set of data is not written into the specific block; and
when the total received data amount of the second set of data reaches the predetermined data amount threshold, reading at least a portion of the second set of data from the volatile memory to directly write the second set of data into the specific block, and directly writing the first set of data into the specific block for a second time.
8. The method of claim 7, further comprising:
respectively receiving a third set of data comprising a plurality of pages from the host device in a page-by-page manner until a total received data amount of the third set of data reaches the predetermined data amount threshold, and temporally storing the third set of data into the volatile memory, wherein before the total received data amount of the third set of data reaches the predetermined data amount threshold, the third set of data is not written into the specific block; and
when the total received data amount of the third set of data reaches the predetermined data amount threshold, reading at least a portion of the third set of data from the volatile memory to directly write the third set of data into the specific block, directly writing the second set of data into the specific block for a second time, and directly writing the first set of data into the specific block for a third time, so that each bit of data of any page of the first set of data is correctly stored into the specific block for further reading.
9. The method of claim 1, further comprising:
before determining to immediately write the received data into the at least one NV memory element:
when at least one read command received from the host device indicates that the host device requests to read at least a portion of the data, reading at least the portion of the data from the volatile memory to respond to the host device, instead of reading at least the portion of the data from the specific NV memory element.
10. The method of claim 1, further comprising:
directly writing the received data into the specific block several times, wherein under control of the controller, a number of times the received data is written into the specific block reaches a predetermined number of times, so that a specific set of memory cells belonging to a specific word-line in the specific block is correctly programmed in the NV memory element, thus making each bit in the received data correctly stored into the specific set of memory cells for further reading.
11. A memory apparatus, comprising:
at least one non-volatile (NV) memory element, each comprising
a plurality of blocks; and
a controller, arranged to control the at least one NV element, the controller comprising a processing unit arranged to manage the memory apparatus according to a program code embedded in the processing unit or received from outside of the processing unit, wherein the controller temporarily stores data received from a host device into a volatile memory in the controller and utilizes the data in the volatile memory as received data, and dynamically monitors a data amount of the received data to determine whether to immediately write the received data into the at least one NV memory element, wherein at least one write command received from the host device indicates that the host device requests to write the data;
wherein when determining to immediately write the received data into the at least one NV memory element, the controller directly writes the received data into a specific block configured to be a Multiple Level Cell (MLC) memory block within a specific NV memory element of the at least one NV memory element, rather than indirectly writes the received data into the specific block by first temporarily writing the received data into any other block configured to be a Single Level Cell (SLC) memory block.
12. The memory apparatus of claim 11, wherein under a situation that a memory cell in the specific block is used to store a plurality of bits, the plurality of bits need to be repeatedly written into the memory cell for a predetermined number of times, so that the memory cell is correctly programmed in the specific NV memory element, thus making each of the plurality of bits correctly stored into the memory cell for further reading; and the predetermined number of times is larger than 1.
13. The memory apparatus of claim 12, wherein when the data amount of the received data reaches a predetermined data amount threshold, the controller determines to immediately write the received data into the at least one NV memory element; and a storage capacity of the volatile memory is not less than a product of the predetermined data amount threshold and the predetermined number of times to allow at least a portion of the received data to be used in a repeated write operation of the memory cell.
14. The memory apparatus of claim 13, wherein the predetermined data amount threshold is equal to a storage capacity of a set of memory cells belonging to a word-line in the specific NV memory element.
15. The memory apparatus of claim 14, wherein any of the plurality of blocks comprises a predetermined number of pages; the controller receives a plurality of sets of data from the host device, respectively, and temporarily stores the plurality of sets of data into the volatile memory, wherein each of the plurality of sets of data comprises a plurality of pages, and a data amount of each of the plurality of sets of data is equal to the predetermined data amount threshold; and the controller reads the plurality of sets of data from the volatile memory to directly write the plurality of sets of data into the specific block, respectively, and directly writes a first set of data of the plurality of sets of data into the specific block several times, wherein a number of times the first set of data is written into the specific block reaches the predetermined number of times, so that a specific set of memory cells belonging to a specific word-line in the specific block is correctly programmed in the specific NV memory element, thus making each bit of the first set of data correctly stored in the specific set of memory cells for further reading.
16. A controller of a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element each comprising a plurality of blocks, the controller comprising:
a processing unit, arranged to manage the memory apparatus according to a program code embedded in the processing unit or received from outside of the processing unit, wherein the controller temporarily stores data received from a host device into a volatile memory in the controller and utilizes the data in the volatile memory as received data, and dynamically monitors a data amount of the received data to determine whether to immediately write the received data into the at least one NV memory element, wherein at least one write command received from the host device indicates that the host device requests to write the data; and
wherein when determining to immediately write the received data into the at least one NV memory element, the controller directly writes the received data into a specific block configured to be a Multiple Level Cell (MLC) memory block within a specific NV memory element of the at least one NV memory element, rather than indirectly writes the received data into the specific block by first temporarily writing the received data into any other block configured to be a Single Level Cell (SLC) memory block.
17. The controller of claim 16, wherein under a situation that a memory cell in the specific block is used to store a plurality of bits, the plurality of bits need to be repeatedly written into the memory cell for a predetermined number of times, so that the memory cell is correctly programmed in the specific NV memory element, thus making each of the plurality of bits correctly stored into the memory cell for further reading; and the predetermined number of times is larger than 1.
18. The controller of claim 17, wherein when the data amount of the received data reaches a predetermined data amount threshold, the controller determines to immediately write the received data into the at least one NV memory element; and a storage capacity of the volatile memory is larger than or equal to a product of the predetermined data amount threshold and the predetermined number of times to allow at least a portion of the received data to be used in a repeated write operation of the memory cell.
19. The controller of claim 18, wherein the predetermined data amount threshold is equal to a capacity of a set of memory cells belonging to a word-line in the specific NV memory element.
20. The controller of claim 19, wherein any of the plurality of blocks comprises a predetermined number of pages; the controller receives a plurality of sets of data from the host device, respectively, and temporarily stores the plurality of sets of data into the volatile memory, wherein each of the plurality of sets of data comprises a plurality of pages, and a data amount of each of the plurality of sets of data is equal to the predetermined data amount threshold; and the controller reads the plurality of sets of data from the volatile memory to directly write the plurality of sets of data into the specific block, respectively, and directly writes a first set of data of the plurality of sets of data into the specific block several times, wherein a number of times the first set of data is written into the specific block reaches the predetermined number of times, so that a specific set of memory cells belonging to a specific word-line in the specific block is correctly programmed in the specific NV memory element, thus making each bit of the first set of data correctly stored in the specific set of memory cell for further reading.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electric machine comprising:
a laminated stack including first and second additively manufactured conductive phase coils, each of the first and second additively manufactured phase coils comprised of a plurality of conductive strands; and
an additively manufactured end winding that conductively couples the first and second phase coils, wherein the end winding has a non-circular cross-sectional geometry.
2. The electric machine of claim 1, wherein the non-circular cross-sectional geometry is quadrilateral.
3. The electric machine of claim 2, wherein the non-circular cross-sectional geometry is rectangular.
4. The electric machine of claim 2, wherein the end winding twists 180\xb0 between the first and second phase coils.
5. The electric machine of claim 1, wherein the additively manufactured end winding has a stair-stepped geometry.
6. The electric machine of claim 2, wherein the end winding further comprises:
first and second linear legs extending from the first and second phase coils, respectively; and
a semicircular bridge arranged perpendicular to the laminated stack, wherein the semicircular bridge is connected to both the first and second linear legs;
wherein the first and second linear legs and the semicircular bridge each comprise a plurality of conductive portions embedded in an insulating material.
7. The electrical machine of claim 1, and further comprising a plurality of slots each containing two phase coils.
8. The electrical machine of claim 7, wherein the two phase coils in each slot are separated from one another by a predetermined minimum distance.
9. The electrical machine of claim 1, wherein the laminated stack has a first height, and the end windings have a second height, and the ratio of the first height to the second height is greater than 6 to 1.
10. An end winding structure for an electric machine having a plurality of conductive phase coils additively manufactured within a laminated stack, the end winding comprising:
a plurality of conductive portions configured to selectively interconnect a plurality of strands of the phase coils;
an insulator material surrounding each of the plurality of conductive portions, wherein a fill factor of the strands comprising the phase coils is greater than 50%.
11. The end winding structure of claim 10, wherein the end winding is arranged along an optimized path.
12. The end winding structure of claim 10, wherein the plurality of conductive portions are arranged in a region that has a non-circular cross-section.
13. The end winding structure of claim 12, wherein the region has a quadrilateral cross-section.
14. The end winding structure of claim 10, wherein the laminated stack has a first height, and the plurality of conductive portions have a second height, and the ratio of the first height to the second height is greater than 6 to 1.
15. The end winding structure of claim 10, wherein the plurality of phase coils are connected by a plurality of end windings in an FSCW pattern.
16. The end winding structure of claim 10, wherein the end winding includes a 180\xb0 twist.
17. The end winding structure of claim 10, wherein the conductive end winding further comprises:
first and second linear legs extending from the first and second phase coils, respectively; and
a semicircular portion arranged perpendicular to the laminated stack, wherein the semicircular portion is connected to both the first and second linear legs.
18. The end winding structure of claim 17, wherein each of the linear legs extend from the laminated stack at an angle 8 that is between 0\xb0 and 90\xb0.
19. The end winding structure of claim 10, wherein at least two end windings are separated from one another by at least a predetermined minimum distance.
20. The end winding structure of claim 19, wherein the distance between any two adjacent end windings is constant.