1. An optical disc apparatus, comprising:
a recording section for recording new data on an optical disc so as to be continuous to data which is previously recorded on the optical disc;
a detection section for detecting an amount of deviation between a position at which the previously recorded data is recorded and a position at which the previously recorded data should have been recorded; and
an adjustment section for adjusting a position at which the new data is to be recorded so that an amount of deviation between a position at which an end of the new data is to be recorded and a position at which the end of the new data should be recorded is smaller than the amount of deviation detected by the detection section.
2. An optical disc apparatus according to claim 1, wherein the adjustment section adjusts the position at which the new data is to be recorded so that the amount of deviation between the position at which the end of the new data is to be recorded and the position at which the end of the new data should be recorded is substantially zero.
3. An optical disc apparatus according to claim 1, wherein:
the recording section records the new data on the optical disc in synchronization with a recording clock; and
the adjustment section adjusts a frequency of the recording clock so as to adjust the position at which the new data is to be recorded.
4. An optical disc apparatus according to claim 1, further comprising reference frequency detection section for detecting a reference frequency of the recording clock, wherein the adjustment section control the frequency of the recording clock so that the frequency of the recording clock approaches the reference frequency.
5. An optical disc apparatus, comprising:
a pre-pit sync detection circuit for detecting a prescribed pre-pit pre-formed on an optical disc and outputting a pre-pit sync detection signal in response to detection of the prescribed pre-pit;
a data sync detection circuit for detecting a prescribed synchronization signal included in the previously recorded data and outputting a data sync detection signal in response to detection of the synchronization signal;
a recording clock generation circuit for generating a recording clock; and
a recording circuit system for recording the new data on the optical disc in synchronization with the recording clock based on the data sync detection signal,
wherein the recording clock generation circuit detects a time-wise amount of deviation between the pre-pit sync detection signal and the data sync detection signal and controls a frequency of the recording clock so as to correct the detected time-wise amount of deviation.
6. An optical disc apparatus according to claim 5, wherein the recording clock generation circuit includes:
a first timing signal generator for generating a first rectangular wave in synchronization with the recording clock based on the pre-pit sync detection signal;
a second timing signal generator for generating a second rectangular wave in synchronization with the recording clock based on the data sync detection signal; and
a control circuit for controlling the frequency of the recording clock so that a phase difference between the first timing signal and the second timing signal approaches zero.
7. An optical disc apparatus according to claim 6, wherein:
the first timing signal generator generates the first rectangular wave by dividing the frequency of the recording clock, and
the second timing signal generator generates the second rectangular wave by dividing the frequency of the recording clock.
8. An optical disc apparatus according to claim 5, wherein the recording clock generation circuit includes:
a first timer which is preset at a first prescribed value in response to the pre-pit sync detection signal;
a second timer which is preset at a second prescribed value in response to the data sync detection signal; and
a control circuit for controlling the truancy of the recording clock so that a difference between a value of the first timer and a value of the second timer approaches zero.
9. An optical disc apparatus according to claim 8, wherein the first timer and the second timer operate in synchronization with the recording clock.
10. An optical disc apparatus according to claim 5, wherein the optical disc has a track formed thereon having wobbles of a prescribed cycle, the optical disc apparatus further comprising a wobble detection circuit for detecting the wobbles and outputting a wobble signal representing a frequency of the wobbles, wherein the recording clock generation circuit controls the frequency of the recording clock in accordance with the wobble signal.
11. An optical disc apparatus according to claim 10, wherein the recording clock generation circuit controls the frequency of the recording clock in accordance with the wobble signal before recording of the new data is started; and controls the frequency of the recording clock in accordance with the wobble signal and the detected time-wise amount of deviation after the recording of the new data is started.
12. An optical disc apparatus according to claim 10, further comprising a reproduction clock generation circuit for generating a reproduction clock from the previously recorded data, wherein the recording clock generation circuit controls the frequency of the recording clock in accordance with the reproduction clock before recording of the new data is started; and controls the frequency of the recording clock in accordance with the wobble signal and the detected time-wise amount of deviation after the recording of the new data is started.
13. An optical disc apparatus according to claim 1, wherein:
the detection section comprises a first timing signal generator and a second timing signal generator;
the position at which the previously recorded data is recorded is detected based on a data sync detection signal; and
the position at which the previously recorded data should have been recorded is detected based on a pre-pit sync detection signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for canceling a read or write operation in a memory system having a plurality of dynamic random access memory (DRAM) devices comprising:
providing address and control information to the plurality of DRAM devices operation through a memory controller to enable a data stream to or from a processor;
masking data by the memory controller, thereby protecting the data stream during read operations if a command cancel signal is received;
generating a command cancel signal to disable the memory system if an incorrect data stream is presented to the DRAM, said command cancel signal being generated within a clocking cycle of the memory system; and
restoring the system in response to the command cancel signal.
2. The method of claim 1 which includes:
monitoring the integrity of read or write operations to a DRAM, and generating a command cancel signal in response to the detection of an incorrect operation.
3. A method for canceling a write or read operation in a memory system having a plurality of DRAM devices comprising:
timing the operations in clock cycles;
providing a write latency of one or more clock cycles between receipt of a write command and receipt of data; and
generating a command cancel signal to disable the write operation at the DRAM subsequent to the initial write command and prior to the write latency of the memory device, without damage to existing stored data.
4. The method of claim 3 wherein the command cancel signal terminates the write operation within the DRAM devices.
5. The method of claim 4 wherein the command cancel signal resets FIFO clocks.
6. The method of claim 3 wherein the command cancel signal is transmitted on a unique pin.
7. The method of claim 3 wherein the command cancel signal is triggered by ECC logic.
8. The method of claim 7 wherein the ECC logic operates in parallel or series mode.
9. The method of claim 8 wherein if an ECC error is detected in parallel mode a re-try operation is performed to determine if a soft error occurred allowing continuous ECC parallel operation.
10. The method of claim 9 wherein if an ECC error is detected which required correction, the ECC mode is changed to serial operation until a repair action is completed.
11. The method of claim 3 wherein the command cancel signal is triggered by a parity bit.