What is claimed is:
1. A method for encoding data read from a multistate memory array comprising cells, where each of the cells has N states, where N is an integer greater than two, and each of the states is indicative of a different stored data bit, said method including the steps of:
(a) generating data signals by reading selected ones of the cells, where each of the data signals has a value indicative of a data bit stored in a different one of the cells, each said value is in a range which is a member of a sequence of ranges LiHi, where i is an integer from 1 through N, each said range LiHi consisting of values xi, where Li<xi<Hi, and where L1<H1<L2<H2< . . . <LN<HN; and
(b) encoding the data signals by replacing each of the data signals with an encoded data signal, where for each of the data signals whose value is in the range LiHi, the encoded data signal is an ordered set of bits Ei, where Em is not identical to En where m and n are different integers in the range from 1 through N, and where for each pair of ordered sets Ej1 and Ej indicative respectively of a first ordered set of bits and a second ordered set of bits, the second ordered set is generated by changing X bits of the first ordered set, where j is an integer in the range from 2 through N, and X is a selected integer.
2. The method of claim 1, wherein X1, so that for each said pair of ordered sets Ej1 and Ej, the second ordered set is generated by changing one bit of the first ordered set.
3. The method of claim 1, wherein each ordered set of bits Ei is an ordered set of binary bits.
4. The method of claim 3, wherein X1, so that for each said pair of ordered sets Ej1 and Ej, the second ordered set is generated by changing one binary bit of the first ordered set.
5. The method of claim 3, wherein N4, and wherein ordered sets Ej, Ej1, Ej2, and Ej3 are indicative, respectively, of ordered binary bit sets 00, 01, 11, and 10.
6. The method of claim 5, where L1 is substantially equal to 0 volts, H1 is substantially equal to 1.2 volts, L2 is substantially equal to 1.25 volts, H2 is substantially equal to 2.45 volts, L3 is substantially equal to 2.5 volts, H3 is substantially equal to 3.7 volts, L4 is substantially equal to 3.75 volts, and H4 is substantially equal to 5.0 volts, and ordered sets E1, E2, E3, and E4 are indicative, respectively, of ordered binary bit sets 00, 01, 11, and 10.
7. The method of claim 3, wherein N8, and wherein ordered sets Ej, Ej1, Ej2, and Ej3, Ej4, Ej5, Ej6, and Ej7 are indicative, respectively, of ordered binary bit sets 000, 001, 011, 010, 110, 111, 101, and 100.
8. The method of claim 3, wherein N8, and wherein ordered sets Ej, Ej1, Ej2, and Ej3, Ej4, Ej5, Ej6, and Ej7 are indicative, respectively, of ordered binary bit sets 000, 100, 101, 001, 011, 111, 110, and 010, respectively.
9. The method of claim 1, also including the steps of:
(c) performing error detection on the encoded data signals generated in step (b), thereby detecting an error in at least one of said encoded data signals; and
(d) correcting the error by changing one bit of the ordered set of bits indicated by said at least one of said encoded data signals.
10. A multistate memory system, including:
a memory array comprising cells, where each of the cells has N states, where N is an integer greater than two, and each of the states is indicative of a different stored data bit;
a first circuit connected to the memory array and configured to read selected ones of the cells thereby generating data signals, where each of the data signals has a value indicative of a data bit stored in a different one of said selected ones of the cells, each said value is in a range which is a member of a sequence of ranges LiHi, where i is an integer from 1 through N, each said range LiHi consisting of values xi, where Li<xi<Hi, and where L1<H1<L2<H2< . . . <LN<HN; and
an encoding unit connected to the first circuit and configured to encode the data signals by replacing each of said data signals with an encoded data signal, where for each of the data signals whose value is in the range LiHi, the encoded data signal is an ordered set of bits Ei, where Em is not identical to En where m and n are different integers in the range from 1 through N, and where for each pair of ordered sets Ej1 and Ej indicative respectively of a first ordered set of bits and a second ordered set of bits, the second ordered set is generated by changing X bits of the first ordered set, where j is an integer in the range from 2 through N, and where X is an integer.
11. The system of claim 10, wherein X1, so that for each said pair of ordered sets Ej1 and Ej, the second ordered set is generated by changing one bit of the first ordered set.
12. The system of claim 10, wherein each ordered set of bits Ei is an ordered set of binary bits.
13. The system of claim 12, wherein X1, so that for each said pair of ordered sets Ej1 and Ej, the second ordered set is generated by changing one bit of the first ordered set.
14. The system of claim 13, wherein N4, and wherein ordered sets Ej, Ej1, Ej2, and Ej3 are indicative, respectively, of ordered binary bit sets 00, 01, 11, and 10.
15. The system of claim 13, where L1 is substantially equal to 0 volts, H1 is substantially equal to 1.2 volts, L2 is substantially equal to 1.25 volts, H2 is substantially equal to 2.45 volts, L3 is substantially equal to 2.5 volts, H3 is substantially equal to 3.7 volts, L4 is substantially equal to 3.75 volts, and H4 is substantially equal to 5.0 volts, and ordered sets E1, E2, E3, and E4 are indicative, respectively, of ordered binary bit sets 00, 01, 11, and 10.
16. The system of claim 13, wherein N8, and wherein ordered sets Ej, Ej1, Ej2, and Ej3, Ej4, Ej5, Ej6, and Ej7 are indicative, respectively, of ordered binary bit sets 000, 001, 011, 010, 110, 111, 101, and 100.
17. The system of claim 13, wherein N8, and wherein ordered sets Ej, Ej1, Ej2, and Ej3, Ej4, Ej5, Ej6, and Ej7 are indicative, respectively, of ordered binary bit sets 000, 100, 101, 001, 011, 111, 110, and 010, respectively.
18. The system of claim 10, also including:
error detection and correction circuitry connected to the encoding unit and configured to perform error detection on the encoded data signals, thereby detecting an error in at least one of said encoded data signals and correcting the error by changing one bit of the ordered set of bits indicated by said at least one of said encoded data signals.
19. The memory system of claim 10, wherein said memory system is an integrated memory circuit, and each of said cells is a flash memory cell.
20. A multistate memory system, including:
a memory array comprising cells, where each of the cells has four states, each of the states is indicative of a different stored data bit, a first of the states is determined by a first voltage range L1H1 between voltages L1 and H1, a second of the states is determined by a second voltage range L2H2 between voltages L2 and H2, a third of the states is determined by a third voltage range L3H3 between voltages L3 and H3, and a fourth of the states is determined by a fourth voltage range L4H4 between voltages L4 and H4, where L1<H1<L2<H2<L3<H3<L4<H4;
a first circuit connected to the memory array and configured to read selected ones of the cells thereby generating data signals, each of the data signals having a voltage in one of said voltage ranges L1H1, L2H2, L3H3, and L4H4; and
an encoding unit connected to the first circuit and configured to encode the data signals by replacing each of said data signals with an encoded data signal, where for each of the data signals whose value is in the range LiHi, the encoded data signal is an ordered set of bits Ei, where i is an integer from 1 through 4, and where for each pair of ordered sets Ej1 and Ej indicative respectively of a first ordered set of bits and a second ordered set of bits, the second ordered set is generated by changing X bits of the first ordered set, where j is an integer in the range from 2 through 4, and X is an integer.
21. The system of claim 20, wherein X1, so that for each said pair of ordered sets Ej1 and Ej, the second ordered set is generated by changing one bit of the first ordered set.
22. The system of claim 20, wherein each ordered set of bits Ei is an ordered set of binary bits.
23. The system of claim 22, wherein X1, so that for each said pair of ordered sets Ej1 and Ej, the second ordered set is generated by changing one bit of the first ordered set.
24. The system of claim 23, wherein ordered sets Ej, Ej1, Ej2, and Ej3 are indicative, respectively, of ordered binary bit sets 00, 01, 11, and 10.
25. The system of claim 20, where L1 is substantially equal to 0 volts, H1 is substantially equal to 1.2 volts, L2 is substantially equal to 1.25 volts, H2 is substantially equal to 2.45 volts, L3 is substantially equal to 2.5 volts, H3 is substantially equal to 3.7 volts, L4 is substantially equal to 3.75 volts, and H4 is substantially equal to 5.0 volts.
26. The system of claim 20, also including:
error detection and correction circuitry connected to the encoding unit and configured to perform error detection on the encoded data signals, thereby detecting an error in at least one of said encoded data signals, and to correct the error by changing one bit of the ordered set of bits indicated by said at least one of said encoded data signals.
27. The memory system of claim 20, wherein each of said cells is a flash memory cell.
28. The memory system of claim 27, wherein said memory system is an integrated memory circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A liquid crystal display comprising:
a couple of substrates disposed facing each other; and
a liquid crystal layer disposed between the pair of substrates, the liquid crystal layer containing liquid crystal molecules having a negative dielectric anisotropy, each pixel in the liquid crystal layer having more than two regions, the liquid crystal molecules in one of the regions having a pre-tilt angle different from that of the liquid crystal in another region.
2. The liquid crystal display according to claim 1, wherein the pre-tilt angle of the liquid crystal molecules is 0\xb0 in one of the regions of the liquid crystal layers.
3. A method of manufacturing a liquid crystal display comprising steps of:
sealing, between a couple of substrates disposed facing each other, a liquid crystal layer composed of a vertical alignment liquid crystal containing monomers;
polymerizing the monomers in a first region within a pixel, with a first voltage applied between the couple of substrates holding the liquid crystal layer in between; and
polymerizing the monomers in a second region within a pixel, with a second voltage different from the first voltage applied between the couple of substrates holding the liquid crystal layer in between.
4. The method of manufacturing a liquid crystal display according to claim 3, wherein one of the first voltage and the second voltage is 0V.