1. A method for converting a plurality of powerlines in at least a building structure into a communication network for a plurality of users, the method comprising:
coupling an apparatus for communicating between a data source and at least one of a plurality of users through a powerline network, the apparatus comprising:
a datasource connection, the datasource connection coupled to a data source;
a powerline device coupled to the datasource connection, the powerline device being adapted to receive and transmit information in a first format from the datasource connection and adapted to receive and transmit information in a second format;
a virtual local area network device including a first inputoutput port and a plurality of second inputoutput ports, each of the second inputoutput ports numbered from 1 through N, where N is an integer greater than 1;
a plurality of modem devices coupled to the virtual local area network device, the plurality of modem devices numbered from 1 through N, each of the plurality of modem devices being coupled respectively to one of the plurality of second inputoutput ports, each of the plurality of modem devices also being coupled to one of a plurality of powerlines numbered from 1 through N, each of the plurality of powerlines being capable of communicating information to and from the data source;
allowing at least one of the users to communicate to the data source through one of the plurality of powerlines; and
denying access to at least one of the users from communicating to the data source through one of the plurality of powerlines.
2. The method of claim 1 wherein the building structure is an office building.
3. The method of claim 1 wherein the building structure is a residential home.
4. The method of claim 1 wherein the building structure is a multi-tenant building.
5. The method of claim 1, and further comprising coupling one or more of the apparatuses in a cascaded deployment, each apparatus serving a plurality of users.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacturing a phase change memory device, comprising:
providing a semiconductor substrate having a cell area and a coreperi area defined therein;
forming a gate of a driving transistor in the coreperi area of the semiconductor substrate;
forming a strain stress supplying layer in the cell area of the semiconductor substrate and in the coreperi area of the semiconductor substrate along opposing sides of the gate;
simultaneously forming a junction word line in the cell area and forming sourcedrain of the driving transistor in the coreperi area by implanting impurities of a first conductivity into the strain stress supplying layer;
forming an interlayer insulating layer over the semiconductor substrate in which the junction word line and the sourcedrain are formed therein; and
forming switching diodes within the interlayer insulating layer that are connected the junction word line.
2. The method of claim 1, wherein the semiconductor substrate comprises a silicon substrate, and the strain stress supplying layer comprises a SiGe layer.
3. The method of claim 1, further comprising forming a buffer layer having a lattice property between that of the semiconductor substrate and that of the strain stress supplying layer on an exposed portion of the semiconductor substrate wherein forming the buffer layer is performed after forming the gate and before forming a strain stress supplying layer.
4. The method of claim 1, wherein the forming switching diodes includes:
forming diode contact holes exposing portions of the junction word line by etching the interlayer insulating layer;
forming a semiconductor layer to fill in the diode contact holes;
implanting impurities of a first conductivity into the semiconductor layer; and
implanting impurities of a second conductivity into the semiconductor layer.
5. The method of claim 4, wherein the forming semiconductor layer includes an epitaxial grown semiconductor layer which uses the junction word line as a base.
6. The method of claim 4, wherein forming the semiconductor layer includes depositing a polysilicon layer.
7. The method of claim 1, further comprising: after the forming switching diodes,
forming heating electrodes contacting the switching diodes;
forming phase change structures contacting the heating electrodes; and
forming a bit line electrically connected to the phase change structures.
8. The method of claim 1, further comprising:
forming phase change material structures contact to the switching diodes; and
forming a bit line electrically connected to the phase change structures, wherein forming the phase change material and the bit line are performed after forming the switching diodes,