1. A semiconductor memory device, comprising:
a memory cell array;
a redundant element;
an address specifying circuit configured to select one of a plurality of addresses as a redundancy address in response to a switchover signal;
a decoder circuit configured to select the redundant element in response to an externally applied address that matches the redundancy address selected by the address specifying circuit; and
a test mode setting circuit configured to change the switchover signal in response to an externally applied input, thereby to cause the redundancy address assigned to the redundant element to be switched between different ones of the plurality of addresses.
2. The semiconductor memory device as claimed in claim 1, wherein the address specifying circuit includes:
a first address specifying circuit configured to specify a first address;
a second address specifying circuit configured to specify a second address; and
a select circuit configured to select one of an output of the first address specifying circuit and an output of the second address specifying circuit in response to the switchover signal.
3. The semiconductor memory device as claimed in claim 2, wherein the first address specifying circuit produces as the output thereof a first bit pattern indicative of bitwise matches or mismatches between the first address and an externally applied address, and the second address specifying circuit produces as the output thereof a second bit pattern indicative of bitwise matches or mismatches between the second address and the externally applied address.
4. The semiconductor memory device as claimed in claim 3, further comprising a memory circuit configured to store a defective address in a nonvolatile manner, and wherein the first address specifying circuit is configured to selectively invert bits of the first bit pattern in response to respective bit values of an output of the memory circuit.
5. The semiconductor memory device as claimed in claim 1, wherein the address specifying circuit includes:
an address specify circuit configured to specify a first address;
a register configured to store an address bit pattern that is externally applied; and
a select circuit configured to select one of the first address and a second address responsive to the address bit pattern stored in the register in response to the switchover signal.
6. The semiconductor memory device as claimed in claim 5, wherein the address specify circuit is configured to produce a bit pattern indicative of bitwise matches or mismatches between the first address and an externally applied address in response to selection of the first address by the select circuit, and to produce a bit pattern obtained by selectively inverting respective bits of the bit pattern indicative of bitwise matches or mismatches depending on respective bit values of the address bit pattern in response to selection of the second address by the select circuit.
7. The semiconductor memory device as claimed in claim 6, further comprising a memory circuit configured to store a defective address in a nonvolatile manner, and wherein the address specify circuit is configured to selectively invert bits of the bit pattern indicative of bitwise matches or mismatches in response to respective bit values of an output of the memory circuit.
8. The semiconductor memory device as claimed in claim 1, wherein the address specifying circuit includes:
an address specify circuit configured to specify a first address;
a pattern specify circuit configured to produce an address bit pattern responsive to an externally applied signal; and
a select circuit configured to select, in response to the switchover signal, one of the first address and a second address that is obtained by modifying a value of the first address in response to the address bit pattern produced by the pattern specify circuit.
9. The semiconductor memory device as claimed in claim 8, wherein the address specify circuit is configured to produce a bit pattern indicative of bitwise matches or mismatches between the first address and an externally applied address in response to selection of the first address by the select circuit, and to produce a bit pattern obtained by selectively inverting respective bits of the bit pattern indicative of bitwise matches or mismatches depending on respective bit values of the address bit pattern in response to selection of the second address by the select circuit.
10. A system, comprising:
a CPU; and
a memory,
wherein the memory includes:
a memory cell array;
a redundant element;
an address specifying circuit configured to select one of a plurality of addresses as a redundancy address in response to a switchover signal;
a decoder circuit configured to select the redundant element in response to an address specified by the CPU that matches the redundancy address selected by the address specifying circuit; and
a test mode setting circuit configured to change the switchover signal in response to instruction from the CPU, thereby to cause the redundancy address assigned to the redundant element to be switched between different ones of the plurality of addresses.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A cytometer system comprising:
a flow channel having an axis;
a hydrodynamic focusing channel connected to the flow channel;
an injection channel connected to the hydrodynamic focusing channel;
a first sheath fluid channel connected to the hydrodynamic focusing channel; and
a second sheath fluid channel connected to the hydrodynamic focusing channel;
2. The system of claim 1, further comprising:
a light source proximate to the flow channel; and
a detector proximate to the flow channel.
3. The system of claim 2, further comprising:
a first pressure control mechanism connected to the first sheath fluid channel; and
a second pressure control mechanism connected to the second sheath fluid channel.
4. The system of claim 3, further comprising a processor connected to the detector, the first pressure control mechanism and the second pressure control mechanism.
5. The system of claim 4, wherein:
the detector may provide a signal to the processor indicating a position of a core stream relative to the axis of the flow channel;
the first and second pressure mechanisms may affect an alignment of the core stream relative to the axis of the flow channel; and
the processor may provide signals to the first and second pressure mechanisms in response to a signal from the detector to effect the alignment of the core stream relative to the axis of the flow channel.
6. The system of claim 5, wherein the signals to the first and second pressure mechanisms in response to the signal from the detector may align the core stream with the axis of the flow channel.
7. A method of alignment for a cytometer, comprising:
providing a sample fluid;
providing a first sheath fluid proximate to the sample fluid;
providing a second sheath fluid proximate to the sample fluid; and
hydrodynamically focusing the sample fluid into a core stream with the first and second sheath fluids into a flow channel.
8. The method of claim 7, further comprising affecting the first and second sheath fluids proximate to the sample fluid to affect an alignment of the core stream relative to the flow channel.
9. The method of claim 8, further comprising differentially affecting flows of the first and sheath fluids to align the core stream with an axis of the flow channel.
10. The method of claim 9, further comprising determining the alignment of the core stream with a light source and detector proximate to the flow channel.
11. The method of claim 10, wherein:
the core stream comprises particles that may scatter light from the light source;
the detector detects the light scattered by the particles; and
a magnitude of scattered light by the particles is indicative of a position of the core stream with the axis of the flow channel.
12. A means for alignment in a cytometer, comprising:
means for providing a sample fluid;
means for providing a plurality of sheathing fluids;
means for hydrodynamically focusing the sample fluid into a core steam with the multitude of sheathing fluids; and
means for individually affecting the flows of the plurality the sheathing fluids to effect an amount of alignment of the core stream with an axis in a flow channel.
13. The means of claim 12, further comprising means for detecting the amount of alignment of the core steam with the axis in the flow channel.
14. The means of claim 13, further comprising means for providing information from the means for detecting the amount of alignment of the core stream to the means for individually affecting the flows of the plurality of the sheathing fluids to maintain an alignment of the core stream.
15. The means of claim 14, wherein:
the core stream comprises particles; and
the particles flow in a single file through the flow channel.
16. A fluid positioning system, comprising:
a hydrodynamic focusing region;
a plurality of sheathing fluid regions proximate to the hydrodynamic focusing region;
a core fluid region proximate to the hydrodynamic focusing region;
an illumination and detection region proximate to the hydrodynamic focusing region; and
a parameter controller proximate to each region of the plurality of sheathing fluid regions.
17. The system of claim 16, wherein a core fluid from the core fluid region is sheathed with a sheathing fluid from each region of the plurality of sheathing fluid regions into a core stream in the hydrodynamic focusing region.
18. The system of claim 17, wherein:
each sheathing fluid from each region of the plurality of regions has a parameter changeable by the parameter controller proximate to the respective region; and
the core stream has a position that is changeable by a variable parameter of at least one sheathing fluid.
19. The system of claim 18, wherein the core stream may be positioned in the illumination and detection region.
20. The system of claim 19, further comprising an interface connecting at least two parameter-controllers to the illumination and detection region for positioning the core stream in the illumination and detection region.