1. Built-in electric air pump for inflatable products, including a housing, a panel cover, an impeller, a motor, an intake, an air valve orifice, an air valve and an air passage part forming a motor chamber, an impeller chamber communicated with said motor chamber and an air passage communicated with said impeller chamber in said housing, wherein an air passage directional chamber is formed by said air passage part, which is the junction of said air passage, said intake and said air valve orifice; an air passage directional valve is mounted within said air passage directional chamber; a motor chamber’s air inlet is located on the wall of said air passage directional chamber; and said air passage directional valve has a heat dissipation and pressure release outlet which is used for pressure release, air exhaust and heat dissipation during the inflation process and used for drawing-in cool air from the environment during the deflation process.
2. Built-in electric air pump according to claim 1, wherein said air passage directional chamber is a cylindrical chamber which communicates with said air passage, said intake, said air valve orifice and said motor chamber.
3. Built-in electric air pump according to claim 2, wherein said air passage directional valve is a cylindrical valve which is associated with said cylindrical chamber, including upper and lower ends, a central rotating shaft and first and second passages which are located between the upper and lower ends and separated by a middle clapboard.
4. Built-in electric air pump according to claim 3, wherein the upper end of said first passage has an air inletoutlet which communicates with said intake.
5. Built-in electric air pump according to claim 3, wherein the upper end of said second passage has a heat dissipation and pressure release outlet which communicates with said second passage and said intake and is used for pressure release, air exhaust and heat dissipation during the inflation process and used for drawing-in cool air from the environment during the deflation process.
6. Built-in electric air pump according to claim 3, wherein a coniform sealing element, a barrier block, a positioning pole and a switch pressing element are mounted around the upper end of said air passage directional valve.
7. Built-in electric air pump according to claim 3, wherein the lower end of said second passage has a convolute pushing element.
8. Built-in electric air pump according to claim 1, further including an additional seal assembly.
9. Built-in electric air pump according to claim 8, wherein said additional seal assembly includes a sealing cover and a sealing ring which are movably mounted on said intake.
10. Built-in electric air pump according to claim 1, wherein said air valve which comprises an air valve sleeve, an air valve spring, an air valve pedestal, an air valve brace, a sealing strip and an air valve mesh enclosure, is mounted on said air valve orifice through an air valve sealing ring.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A NAND non-volatile two-bit memory cell comprising:
a cell stack and two select stacks disposed on an active area of a substrate, each select stack respectively disposed on a side of the cell stack with a sidewall between the cell stack and a respective select stack;
wherein the cell stack comprises a first dielectric layer disposed over the substrate, a charge accumulation layer capable of holding charge in a portion thereof to store information disposed over the first dielectric layer, a second dielectric layer disposed over the charge accumulation layer and a control gate disposed over the second dielectric layer, and the select stack comprises a third dielectric layer disposed over the substrate and a select gate disposed over the third dielectric layer, the select gate being capable of inverting an underneath channel region to function as a source or a drain of the memory cell.
2. The memory cell of claim 1, wherein the memory cell is programmed by source side injection of electrons.
3. The memory cell of claim 1, wherein the charge accumulation layer comprises a nonconductive material.
4. The memory cell of claim 1, wherein the charge accumulation layer comprises silicon nitride whose thickness is approximately 60-80 angstroms.
5. The memory cell of claim 1, wherein each side of the charge accumulation layer can separately retain charge to store one bit of information.
6. The memory cell of claim 1, wherein the select gate comprises polysilicon.
7. The memory cell of claim 1, wherein the side wall comprises an inner layer of silicon nitride and an outer layer of silicon dioxide.
8. A NAND non-volatile two-bit memory cell array comprising:
a plurality of memory cells arranged in rows and columns, the memory cells in the same column connected in a series to form a cell string;
a plurality of select transistors, each end of the cell string respectively connected to one select transistor; and
a plurality of bit line pairs, each bit line pair including an even bit line and an odd bit line, the even bit line connected to both select transistors disposed at one end of two adjoining cell strings, the odd bit line connected to both select transistors disposed at an opposite end of the same two adjoining cell strings;
wherein the memory cell comprises a cell stack and two select stacks disposed on a substrate, the select stacks respectively disposed on each side of the cell stack with a sidewall between the cell stack and a respective select stack, a select stack disposed between two cell stacks being shared by two adjoining memory cell, the cell stack comprising a first dielectric layer disposed over the substrate, a charge accumulation layer capable of holding charge in a portion thereof to store information disposed over the first dielectric layer, a second dielectric layer disposed over the charge accumulation layer and a control gate disposed over the second dielectric layer, the select stack comprising a third dielectric layer disposed over the substrate and a select gate disposed over the third dielectric layer, the select gate being capable of inverting an underneath channel region to function as a source or a drain of the memory cell.
9. The memory cell array of claim 8, wherein electrons are injected into a portion of the charge accumulation layer by source side injection during a programming operation.
10. The memory cell array of claim 8, wherein the charge accumulation layer comprises a nonconductive material.
11. The memory cell array of claim 8, wherein the charge accumulation layer comprises silicon nitride whose thickness is approximately 60-80 angstroms.
12. The memory cell array of claim 8, wherein each side of the charge accumulation layer can separately retain charge to store one bit of information.
13. The memory cell array of claim 8, wherein the side wall comprises an inner layer of silicon nitride and an outer layer of silicon dioxide.
14. The memory array of claim 8, wherein a selected side of a selected memory cell in a selected cell string is programmed by applying a voltage of approximately 9V to the control gate of the selected cell memory, applying a voltage of approximately 1.5V to the select gate at the selected side, applying a voltage of approximately 7V to other control gates and select gates, and applying a voltage difference of approximately 4.5V across two ends of the selected cell string.
15. The memory cell array of claim 8, wherein each cell string has 16, 32 or 64 memory cells.
16. The memory cell array of claim 8 further comprising a plurality of depletion mode transistors.
17. A method for fabricating a NAND non-volatile two-bit memory cell array, comprising steps of:
forming a first dielectric layer over an active layer in a substrate;
forming a non-conductive layer for charge accumulation layers over the first dielectric layer;
forming a second dielectric layer over the non-conductive layer;
forming a first conductive layer for control gates over the second dielectric layer;
patterning the non-conductive layer, the second dielectric layer and the first conductive layer to form cell stacks;
forming two-layer side walls adjacent to both sides of each cell stack to prevent the control gates from being oxidized in the process; and
forming a second conductive layer for select gates.
18. The method for fabricating a NAND non-volatile two-bit memory cell array of claim 14, wherein the two-layer side wall comprises an inner layer made of silicon nitride and an outer layer made of silicon dioxide.
19. The method for fabricating a NAND non-volatile two-bit memory cell array of claim 15, wherein the inner layer has a thickness of approximately 30 angstroms and the outer layer has a thickness of approximately 150 angstroms.
20. The method for fabricating a NAND non-volatile two-bit memory cell array of claim 14, further comprising steps of:
forming depletion mode transistors; and
forming even-string select transistors and odd-string select transistors.