1. An optical roundabout comprising:
three internal optical switching elements arranged in a ring, each internal optical switching element having two input ports routable to two output ports, the routing of the first input of each internal optical switch being ganged to the routing of the second input for that switch;
each internal optical switching element’s two input ports including an add port and a roundabout-in port; and
each internal optical switching element’s two output ports including a drop port and a roundabout-out port;
wherein the roundabout-out port of each optical switching element is connected to the roundabout-in port of its next optical switching element around the ring by an optical waveguide.
2. The optical roundabout of claim 1 further comprising three external connections arranged in a ring, each external connection having a drop output port in optical communication with the drop output port of a corresponding internal optical switching element and an add input port in optical communication with the add input port of the next optical switching element around the ring from said corresponding internal optical switching element, each internal optical switching element having a single-hop unidirectional switching state for routing optical signals from the add port of each external connection to the drop port of its next external connection around the ring.
3. The optical roundabout of claim 1 further comprising three external connections arranged in a ring, each external connection having a drop output port in optical communication with the drop output port of a corresponding internal optical switching element and an add input port in optical communication with the add input port of the next optical switching element around the ring from said corresponding internal optical switching element, each internal optical switching element having a double-hop unidirectional switching state for routing optical signals from its add port to the drop port of the previous internal optical switching element around the ring.
4. The optical roundabout of claim 1 further comprising three external connections, each external connection having a drop output port in optical communication with the drop output port of a corresponding internal optical switching element and an add input port in optical communication with the add input port of the next optical switching element around the ring from said corresponding internal optical switching element, the optical roundabout having at least one bidirectional switching state for routing optical signals between two external connections wherein two of the internal optical switching elements are in a first switching state and one of the internal optical switching elements is in a second switching state.
5. The optical roundabout of claim 1 further comprising three external connections arranged in a ring, each external connection having a drop output port in optical communication with the drop output port of a corresponding internal optical switching element and an add input port in optical communication with the add input port of said corresponding internal optical switching element, each internal optical switching element having a single-hop unidirectional switching state for routing optical signals from the add port of each external connection to the drop port of its next external connection around the ring.
6. The optical roundabout of claim 1 further comprising three external connections arranged in a ring, each external connection having a drop output port in optical communication with the drop output port of a corresponding internal optical switching element and an add input port in optical communication with the add input port of said corresponding internal optical switching element, the optical roundabout having at least one bidirectional switching state for routing optical signals between two external connections wherein two of the internal optical switching elements are in a first switching state and one of the internal optical switching elements is in a second switching state.
7. The optical roundabout switch of claim 1 further comprising a variable optical attenuator connected to a port of one of the internal optical switching elements.
8. The optical roundabout switch of claim 1 further comprising a multiplexer having an output port in optical communication with an add port of one of the three internal optical switching elements.
9. The optical roundabout switch of claim 1 further comprising a demultiplexer having an input port in optical communication with the drop port of one of the three internal optical switching elements.
10. The optical roundabout switch of claim 1 wherein the second input of the first switch is connected to the output of a multiplexer, and the second output of the first switch is connected to the input of a demultiplexer.
11. An optical roundabout switch comprising:
M optical (M\u22121)\xd7(M\u22121) optical cross-connects, where M is at least three, each optical cross-connect having an (M\u22121)th input for adding an optical signal, and an (M\u22121)th output for dropping an optical signal;
M\u22122 optical waveguides connecting the first M\u22122 outputs of the Nth optical cross-connect to the first M\u22122 inputs of the (N+1)th optical cross connect, for 1\u2266N\u2266M\u22121; and
M\u22122 optical waveguides connecting the first M\u22122 outputs of the Mth optical cross-connect to the first M\u22122 inputs of the first optical cross connect.
12. An optical roundabout switch comprising:
four optical switch modules arranged in a ring, each optical switch module comprising:
a first internal optical switching element and a second optical switching element, each of said first and second optical switching elements having:
first and second inputs, and
first and second outputs,
a selective dropping means for selectably dropping an optical signal from the first output of either of the first optical switch or the second optical switch, and
a selective adding means for selectably adding an optical signal to the second input of either the first optical switch or the second optical switch; and
wherein the routing of the first input within each of the optical switching elements is ganged to the routing of the second input for that optical switching element;
an optical waveguide connecting the second output of the first optical switching element of each optical switch module to the first input of the first optical switching element of a next optical switch module around the ring; and
an optical waveguide connecting the second output of the second optical switching element of each optical switch module to the first input of the second optical switching element of the next optical switch module around the ring.
13. The optical roundabout switch of claim 12 wherein the selective adding means of the first optical switching module is connected to the output of a multiplexer, and the selective dropping means of the first optical switching module is connected to the input of a demultiplexer.
14. The optical roundabout switch of claim 12 wherein the selective adding means of the first optical switching module is connected to the output of a multiplexer, the selective dropping means of the first optical switching module is connected to the input of a demultiplexer, the selective adding means of the third optical switching module is connected to the output of a multiplexer, and the selective dropping means of the third optical switching module is connected to the input of a demultiplexer.
15. The optical roundabout switch of claim 11 further comprising a variable optical attenuator connected to a port of one of the internal optical switching elements.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer, each pillar structure forming a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface;
implanting a hardening species into the vertical pillar transistor top surface;
oxidizing the vertical pillar transistor side surface to form a side surface oxide layer; and
removing the side surface oxide layer to form vertical pillar transistor having rounded side surfaces.
2. The method according to claim 1 wherein the top surface is substantially planar.
3. The method according to claim 1 wherein the hardening species is nitrogen.
4. The method according to claim 1 wherein the removing step selectively removes the side surface oxide layer.
5. The method according to claim 1 wherein the top surface is a parallel with the major surface of the semiconductor wafer.
6. The method according to claim 1 wherein the top surface and the rounded side surfaces form a sharp edge.
7. The method according to claim 1 further comprising a memory cell in electrical connection with the vertical pillar transistor.
8. The method according to claim 7 wherein the memory cell comprises an RRAM memory cell or a spin-torque transfer memory cell.
9. The method according to claim 7 wherein the memory cell comprise an array of memory cells.
10. The method according to claim 1 further comprising forming a gate oxide layer on the rounded side surfaces.
11. A method comprising:
providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer, each pillar structure forming a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface;
implanting a hardening species into the vertical pillar transistor top surface;
oxidizing the vertical pillar transistor forming a top surfaces oxide material layer and a side surface oxide material layer, wherein the top surfaces oxide material layer is different than the side surface oxide material layer; and
removing selectively the side surface oxide material layer to form vertical pillar transistor having rounded side surfaces and the top surfaces oxide material layer.
12. The method according to claim 11 wherein the hardening species is nitrogen.
13. The method according to claim 11 wherein the top surface is a parallel with the major surface of the semiconductor wafer.
14. The method according to claim 11 wherein the top surface and the rounded side surfaces form a sharp edge.
15. The method according to claim 11 further comprising a memory cell in electrical connection with the vertical pillar transistor.
16. The method according to claim 15 wherein the memory cell comprises a spin-torque transfer memory cell.
17. The method according to claim 15 wherein the memory cell comprise an array of memory cells.
18. The method according to claim 11 further comprising forming a gate oxide layer on the rounded side surfaces.
19. A method comprising:
providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer, each pillar structure forming a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface, the vertical pillar transistor having a drain, source and channel regions vertically stacked on top of each other and extending away from the semiconductor wafer;
implanting a hardening species into the vertical pillar transistor top surface and not into the vertical pillar transistor side surface;
oxidizing the vertical pillar transistor forming a top surfaces oxide material layer and a side surface oxide material layer, wherein the top surfaces oxide material layer is different than the side surface oxide material layer;
removing selectively the side surface oxide material layer to form vertical pillar transistor having rounded side surfaces and the top surfaces oxide material layer; and
electrically coupling a memory cell with the vertical pillar transistor.
20. The method according to claim 19 wherein the vertical pillar transistor separated the memory cell from the semiconductor wafer.
21. An apparatus comprising:
a vertical pillar transistor extending orthogonally from a semiconductor wafer, the vertical pillar transistor comprising a planar top surface and rounded side surfaces, the rounded side surfaces are orthogonal to the planar top surface, wherein the top surface includes a hardening implant species;
an electrically conductive gate material layer on the rounded side surfaces; and
a memory cell in electrical connection with the vertical pillar transistor.
22. The apparatus according to claim 21 wherein the memory cell is a STRAM memory cell.
23. The apparatus according to claim 21 wherein the memory cell is electrically between the vertical pillar transistor and the semiconductor wafer.
24. The apparatus according to claim 21 wherein the vertical pillar transistor is electrically between the memory cell and the semiconductor wafer.
25. The apparatus according to claim 21 further comprising a gate oxide layer between the rounded side surfaces and the electrically conductive gate material layer.
26. The apparatus according to claim 21 further comprising a plurality of vertical pillar transistor extending orthogonally from a semiconductor wafer, wherein at least selected vertical pillar transistors comprise a planar top surface and rounded side surfaces, the rounded side surfaces are orthogonal to the planar top surface, wherein the top surface includes a hardening implant species., and an electrically conductive gate material layer is on the rounded side surfaces, and a plurality of memory cells forming a memory array, where each memory cell is in electrical connection with a selected vertical pillar transistor.