1. A non-volatile memory structure, comprising:
a NROM memory array having a plurality of NROM cells organized by rows and columns, a first column of NROM cells having a first NROM cell and a second NROM cell, the first NROM cell having a first node, a second node and a third node, the second NROM cell having a first node, a second node and a third node;
a first metal bit line connecting to the second node of the first NROM cell and the second node of the second NROM cell; and
a second metal bit line connecting to a third node of the first NROM cell and the third node of the second NROM cell;
wherein during an erase operation of the second node, the second node of the first NROM cell and the second node of the second NROM are connected a positive voltage, the third node of the first NROM cell and the third node of the second NROM cell are connected to a common node; and
wherein during an erase operation of the third node, the second node of the first NROM cell and the second node of the second NROM are connected the common node, the third node of the first NROM cell and the third node of the second NROM cell are connected to the positive voltage.
2. The memory structure of claim 1 wherein the common node has a voltage level that is sufficiently high to prevent punch-through yet sufficiently low to maintain a lateral electrical field for erase operation.
3. The memory structure of claim 1 further comprising a discharge system that couples to the NROM memory array for discharging to the common node.
4. The memory structure of claim 3 further comprising a first wordline voltage connecting to the first node of the first NROM cell.
5. The memory structure of claim 4 further comprising a second wordline voltage connecting to the first node of the second NROM cell.
6. The memory structure of claim 5 further comprising an x-decoder for decoding a plurality of metal bit lines that couple to the plurality of NROM cells.
7. The memory structure of claim 6 further comprising a y-decoder for decoding the plurality of metal bit lines that couple to the plurality of NROM cells.
8. The memory structure of claim 7 further comprising a power supply that couples to the y-decoder for supplying a voltage to the plurality of metal bit lines.
9. A non-volatile memory structure, comprising:
a NROM memory array having a plurality of NROM cells organized by rows and columns, a first column of NROM cells having a first NROM cell and a second NROM cell, the first NROM cell having a first node, a second node and a third node, the second NROM cell having a first node, a second node and a third node;
a first metal bit line connecting to the second node of the first NROM cell and the second node of the second NROM cell; and
a second metal bit line connecting to a third node of the first NROM cell and the third node of the second NROM cell;
wherein during an erase operation of the second node, the second node of the first NROM cell and the second node of the second NROM are connected a positive voltage, the third node of the first NROM cell and the third node of the second NROM cell are connected to a current source; and
wherein during an erase operation of the third node, the second node of the first NROM cell and the second node of the second NROM are connected the current source, the third node of the first NROM cell and the third node of the second NROM cell are connected to the positive voltage.
10. The memory structure of claim 9 further comprising a discharge system that couples to the NROM memory array for discharging to the common node.
11. The memory structure of claim 10 further comprising a first wordline voltage connecting to the first node of the first NROM cell.
12. The memory structure of claim 11 further comprising a second wordline voltage connecting to the first node of the second NROM cell.
13. The memory structure of claim 12 further comprising an x-decoder for decoding a plurality of metal bit lines that couple to the plurality of NROM cells.
14. The memory structure of claim 13 further comprising a y-decoder for decoding a plurality of metal bit lines that couple to the plurality of NROM cells.
15. The memory structure of claim 14 further comprising a power supply that couples to the y-decoder for supplying a voltage to the plurality of metal bit lines.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of bonding two wafers having a bonded surface area comprising:
providing a first wafer having a substantially out-gassed oxide layer formed on a surface thereof, said oxide layer being formed at a temperature T1;
providing a second wafer having a surface;
treating the substantially out-gassed oxide layer of the first wafer and the surface of the second wafer with a solution containing NH4OH;
contacting the treated surfaces with each other; and
annealing the two wafers at a temperature T2 which is less than or equal to T1 thereby forming a bonded wafer pair which has a surface energy of about 2000 mJm2 or greater and a bonded interface that has a dislocation density of less than 106 cm\u22122 and a voidbubble density of less than about 1% of the bonded surface area.
2. The method of claim 1 wherein said out-gassed oxide layer is formed by oxidation followed by annealing.
3. The method of claim 1 wherein said out-gassed oxide layer is formed by deposition followed by annealing.
4. The method of claim 1 wherein T1 is equal to or less than 400\xb0 C.
5. The method of claim 1 wherein T1 is from about room temperature to about 300\xb0 C.
6. The method of claim 1 wherein said substantially out-gassed oxide layer contains little or no surface hydroxyl groups andor physisorbed water.
7. The method of claim 1 wherein said substantially out-gassed oxide layer and said surface are polished prior to said treating to provide surfaces having a root mean square surface roughness of less than about 0.5 nm.
8. The method of claim 1 wherein said treating is performed at about room temperature.
9. The method of claim 1 wherein a drying step is performed between said treating and said annealing.
10. The method of claim 1 wherein a rinsing step and a drying step are performed between said treating and said annealing.
11. The method of claim 1 wherein T2 is equal to or less than 400\xb0 C.
12. The method of claim 1 wherein T2 is from about room temperature to about 300\xb0 C.
13. The method of claim 1 wherein said annealing is performed in an inert gas ambient.
14. The method of claim 1 wherein an external force is applied during said contacting and said annealing.