What is claimed:
1. A method for manufacturing a semiconductor device, the semiconductor device having a DRAM including a cell capacitor formed in a DRAM region of a semiconductor substrate, and a capacitor element formed in an analog element region of the semiconductor substrate, the method comprising the steps of:
(a) simultaneously forming a bit line that is a component of the DRAM and a connection layer that is located in a common layer with the bit line and this is used to electrically connect a lower electrode of the capacitor element and another semiconductor element;
(b) simultaneously forming a storage node of the cell capacitor and the lower electrode;
(c) simultaneously forming a dielectric layer of the cell capacitor and a dielectric layer of the capacitor element; and
(d) simultaneously forming a cell plate of the cell capacitor and an upper electrode of the capacitor element.
2. A method for manufacturing a semiconductor device according to claim 1, further comprising the step of:
(e) forming a first resistance element and a second resistance element in the analog element region,
wherein the step (e) is carried out simultaneously with the step (d), and wherein a number of ion-implantations of impurity in a region where the first resistance element is to be formed is greater than a number of ion-implantation of impurity in a region where the second resistance element is to be formed so that a resistance value of the first resistance element is lower than a resistance value of the second resistance element.
3. A method for manufacturing a semiconductor device according to claim 1, further comprising the step of:
(e) forming a first resistance element and a second resistance element in the analog element region,
wherein the step (e) is carried out simultaneously with the step (d), and
wherein an impurity is diffused in a region where the first resistance element is to be formed so that a resistance value of the first resistance element is lower than a resistance value of the second resistance element.
4. A method for manufacturing a semiconductor device according to claim 1, further comprising the step of:
(e) forming a first resistance element and a second resistance element in the analog element region,
wherein the step (e) is carried out simultaneously with the step (d), and
wherein a silicide layer is formed in a region where the first resistance element is to be formed so that a resistance value of the first resistance element is lower than a resistance value of the second resistance element.
5. A semiconductor device having a DRAM including a cell capacitor formed in a DRAM region of a semiconductor substrate, and a capacitor element formed in an analog element region of the semiconductor substrate, the semiconductor device comprising:
an interlayer dielectric layer, an embedded connection layer and a connection layer,
wherein the interlayer dielectric layer is located between the semiconductor substrate and the capacitor element,
the connection layer and the embedded connection layer are used to electrically connect a lower electrode of the capacitor element to another semiconductor element,
the connection layer is located in a common layer of a bit line that is a component of the DRAM,
the embedded connection layer is located in a connection hole formed in the interlayer dielectric layer,
one end of the embedded connection layer connects to the lower electrode at a bottom surface of the lower electrode, and
another end of the embedded connection layer connects to the connection layer.
6. A semiconductor device according to claim 5, further comprising
an additional capacitor element,
wherein the additional capacitor element is located in the analog element region, and
the capacitor element and the additional capacitor element are serially connected to each other by the embedded connection layer and the connection layer.
7. A semiconductor device according to claim 5, further comprising a first resistance element and a second resistance element,
wherein the first resistance element and the second resistance element are located in the analog element region, and
an impurity concentration of the first resistance element is higher than an impurity concentration of the second resistance element so that a resistance value of the first resistance element is lower than a resistance value of the second resistance element.
8. A semiconductor device according to claim 6, further comprising a first resistance element and a second resistance element,
wherein the first resistance element and the second resistance element are located in the analog element region, and
an impurity concentration of the first resistance element is higher than an impurity concentration of the second resistance element so that a resistance value of the first resistance element is lower than a resistance value of the second resistance element.
9. A semiconductor device according to claim 5, further comprising a first resistance element and a second resistance element,
wherein the first resistance element and the second resistance element are located in the analog element region, and
the first resistance element includes a silicide layer so that a resistance value of the first resistance element is lower than a resistance value of the second resistance element.
10. A semiconductor device according to claim 6, further comprising a first resistance element and a second resistance element,
wherein the first resistance element and the second resistance element are located in the analog element region, and
the first resistance element includes a silicide layer so that a resistance value of the first resistance element is lower than a resistance value of the second resistance element.
11. A semiconductor device according to claim 5, wherein a thickness of a dielectric layer of the capacitor element is identical with a thickness of a dielectric layer of the cell capacitor.
12. A semiconductor device according to claim 6, wherein a thickness of a dielectric layer of the capacitor element is identical with a thickness of a dielectric layer of the cell capacitor.
13. A semiconductor device according to claim 7, wherein a thickness of a dielectric layer of the capacitor element is identical with a thickness of a dielectric layer of the cell capacitor.
14. semiconductor device according to claim 9, wherein a thickness of a dielectric layer of the capacitor element is identical with a thickness of a dielectric layer of the cell capacitor.
15. A method for manufacturing a semiconductor device, the semiconductor device having a DRAM including a cell capacitor formed in a DRAM region of a semiconductor substrate, and a capacitor element formed in an analog element region of the semiconductor substrate, the method comprising:
forming a first conducting layer and etching a portion of the first conducting layer to form a bit line that is a component of the DRAM and a connection layer that is located in a common layer with the bit line and used to electrically connect a lower electrode of the capacitor element and another semiconductor element;
forming a second conducting layer and etching a portion of the second conducting layer to form a storage node of the cell capacitor and the lower electrode;
forming a dielectric layer and etching a portion of the dielectric layer to form a dielectric layer of the cell capacitor and a dielectric layer of the capacitor element; and
forming a third conducting layer and etching a portion of the third conducting layer to form a cell plate of the cell capacitor and an upper electrode of the capacitor element.
16. A method according to claim 15, further comprising forming a first resistance element and a second resistance element in the analog element from the third conducting layer, wherein the first resistance element and second resistance element are formed so that a resistance value of the first resistance element is lower than a resistance value of the second resistance element.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit (IC) with an on-die compensation network, comprising:
a compensation inductor of the IC, such that one terminal of the compensation inductor is coupled to a bump pad; and
a metal layer underneath the compensation inductor, such that another terminal of the compensation inductor is coupled to the metal layer of the IC, wherein the metal layer routes input and output signals from the integrated circuit, and wherein the compensation inductor is coupled in a pi-configuration on the IC to compensate for capacitances of the bump pad and the metal layer.
2. The integrated circuit of claim 1, wherein the pi configuration further comprises:
the compensation inductor coupled to a capacitance of the bump pad and a capacitance of the metal layer underneath the compensation inductor.
3. The integrated circuit of claim 1, wherein a value of the compensation inductor is determined by a capacitance of the bump pad and the metal layer, and a capacitance and an inductance of a package and a printed circuit board coupled to the bump pad.
4. The integrated circuit of claim 1, wherein the compensation inductor is located underneath the bump pad.
5. The integrated circuit of claim 1, wherein the compensation inductor is implemented as a spiral inductor.
6. The integrated circuit of claim 1, wherein the compensation inductor is implemented using an existing metal layer closest to a metal layer of the bump pad.
7. The integrated circuit of claim 5, wherein the compensation inductor is implemented using a plurality of metal layers.
8. The integrated circuit of claim 1, wherein the pi-configuration minimizes return loss and insertion loss due to on-die, package, and printed circuit board parasitics.
9. The integrated circuit of claim 1, wherein the bump pad is coupled to one of a wirebond or a solder bump.
10. An electronic module with an on-die compensation network, comprising:
a printed circuit board;
a package coupled to the printed circuit board; and
an integrated circuit coupled to the package, such that the package transmits input and receives output from the printed circuit board to the integrated circuit, the integrated circuit having an on-die matching network compensating for an inductance and a capacitance of the printed circuit board and the package.
11. The electronic module of claim 10, wherein the on-die matching network further comprises:
a compensation inductor coupled in a pi-configuration to a bump pad and a metal layer underneath the compensation inductor.
12. The electronic module of claim 10, wherein the on-die matching network minimizes loss based on parasitics of the integrated circuit, the package, and the printed circuit board.
13. The electronic module of claim 11, wherein a value of the compensation inductor of the on-die matching network is determined by a capacitance of the bump pad and the metal layer, and a capacitance and an inductance of the package and the printed circuit board.
14. The electronic module of claim 11, wherein a diameter of the compensation inductor is less than a diameter of the bump pad.
15. The electronic module of claim 11, wherein the metal layer routes input and output from the integrated circuit to the bump pad.
16. A method of designing an integrated circuit with an on-die compensation network, comprising:
determining a capacitive and an inductive impedance value associated with a printed circuit board and a capacitive and an inductive impedance value associated with a package;
determining a capacitive impedance value associated with a bump pad of the integrated circuit, and an on-die capacitive impedance value associated with the integrated circuit;
calculating a size of a compensation inductor according to the impedance values of the printed circuit board, the package, the bump pad of the integrated circuit, and the integrated circuit;
coupling the compensation inductor to the bump pad and a metal layer of the integrated circuit in a pi-configuration, wherein the metal layer routes input and output from the integrated circuit; and
storing a design of the integrated circuit for manufacturing.
17. The method of claim 16, wherein coupling the compensation inductor further comprises:
calculating a number of turns of the compensation inductor based on the impedance values of the printed circuit board and the package.
18. The method of claim 16, wherein coupling the compensation inductor further comprises:
implementing the compensation inductor on a plurality of metal layers of the integrated circuit closest to the bump pad.
19. The method of claim 16, wherein coupling the compensation inductor further comprises:
placing the compensation inductor underneath the bump pad.
20. The method of claim 16, further comprising:
fabricating the compensation inductor with a diameter less than a diameter of a solder pad.