1. A DC backup power supply system having a plurality of loads to which AC from a commercial power source is supplied, and DC power storage means for supplying DC power to the plurality of the loads at the time of a power outage of the commercial power source, said DC backup power supply system comprising:
a control circuit having a first DC backup output for supplying a power from the DC power storage means to the plurality of the loads, including a specific load, only during the power outage of the commercial power source, and a second DC backup output for continuously supplying a power from the DC power storage means to the specific load regardless of the power outage of the commercial power source or sound operation thereof, the control circuit supplying the respective powers from the same DC power storage means to the first and second DC backup outputs.
2. A DC backup power supply system according to claim 1, wherein a line for the first DC backup output toward the plurality of the loads is a two-way output line through which recharging or discharging of the DC power storage means can be carried out.
3. A DC backup power supply system according to claim 1, wherein the control circuit supplies the first DC backup output from the DC power storage means to the plurality of the loads in response to the power outage of the commercial power source, and stops the first DC backup output upon passage of a predetermined time.
4. A DC backup power supply system according to claim 1, wherein a power capacity of the first DC backup output to the plurality of the loads, is not less than ten times as large as the power capacity of the second DC backup output to the specific load.
5. A DC backup power supply system according to claim 1, wherein a duration of the first DC backup output is not more than one tenth of a duration of the second DC backup output.
6. A DC backup power supply system according to claim 1, wherein the control circuit supplies the first DC backup output from the DC power storage means to the plurality of the loads in response to the power outage of the commercial power source, and stops the first DC backup output in response to a signal from the loads.
7. A DC backup power supply system according to claim 1, wherein the specific load comprises a cache memory or a non-volatile memory, andor a DCDC converter for supplying DC power to the memory.
8. A DC backup power supply system having an ACDC converter for receiving AC from a commercial power source, and supplying DC power to a plurality of loads, and DC power storage means for supplying DC power to the plurality of the loads at the time of a power outage of the commercial power source, said DC backup power supply system comprising:
a control circuit having a first DC backup output for supplying a power from the DC power storage means to the plurality of the loads, including a specific load, only during the power outage of the commercial power source, and for stopping thereafter the first DC backup output upon passage of a predetermined time, andor in response to a predetermined signal, and having a second DC backup output for continuously supplying a power from the DC power storage means to the specific load regardless of the power outage of the commercial power source or sound operation thereof, the control circuit supplying the respective powers from the same DC power storage means to the first and second DC backup outputs.
9. A DC backup power supply system according to claim 8, wherein a line for the first DC backup output toward the plurality of the loads is a two-way output line through which recharging or discharging of the DC power storage means can be carried out.
10. A DC backup power supply system according to claim 8, wherein a power capacity of the first DC backup output to the plurality of the loads, is not less than ten times as large as a power capacity of the second DC backup output to the specific load.
11. A DC backup power supply system according to claim 8, wherein a duration of the first DC backup output is not more than one tenth of a duration of the second DC backup output.
12. A DC backup power supply system according to claim 8, wherein the control circuit supplies the first DC backup output from the DC power storage means to the plurality of the loads in response to the power outage of the commercial power source, and stops the first DC backup output in response to a signal from the loads.
13. A DC backup power supply system according to claim 8, wherein the specific load comprises a cache memory or a non-volatile memory, andor a DCDC converter for supplying DC power to the memory.
14. A DC backup power supply system according to claim 8, wherein the specific load receives the first DC backup output via a diode, and receives the second DC backup output via a plurality of diodes.
15. A DC backup power supply system according to claim 8, wherein the DC power storage means comprise a plurality of secondary battery groups connected in parallel, each composed of a plurality of secondary batteries connected in series, including a secondary battery group different in kind from other secondary battery groups.
16. A DC backup power supply system according to claim 15, comprising the secondary battery group having a different discharge rate from the other secondary battery groups.
17. A DC backup power supply system according to claim 8, wherein the control circuit comprises a charger for supplying power to the DC power storage means, first and second output circuits for passing the first and second DC backup outputs from the DC power storage means, respectively, a latch circuit for controlling the second output circuit, an auxiliary power source as the power source of the latch circuit, and a CPU for controlling the charger, the output circuits, the latch circuit, and the auxiliary power source.
18. A DC backup power supply system according to claim 17, wherein power is supplied from the auxiliary power source to the latch circuit during supply of the second DC backup output to the specific load at the time of the power outage of the commercial power source, and while power supply to other circuits within the control circuit is stopped, the latch circuit is configured so as to interrupt the second output circuit in response to a predetermined instruction.
19. A disk array having an ACDC converter for receiving AC from a commercial power source to be converted into DC, a CPU to which DC output from the ACDC converter is supplied, a plurality of loads including a cache memory, and a plurality of hard disk drives, and DC power storage means for supplying DC power to the plurality of the loads at the time of a power outage of the commercial power source, said disk array comprising:
a control circuit having a first DC backup output for supplying a power from the DC power storage means to the plurality of the loads, including the cache memory until a predetermined time or a predetermined signal is received, only during the power outage of the commercial power source, and a second DC backup output for continuously supplying a power from the DC power storage means to the cache memory regardless of the power outage of the commercial power source or sound operation thereof, the control circuit supplying the respective powers from the same DC power storage means to the first and second DC backup outputs.
20. A disk array according to claim 19, comprising a plurality of DCDC converters for stepping down the first and second DC backup outputs to be thereby supplied to the CPU, the hard disk drives, andor the cache memory, respectively.
21. A DC backup power supply system having DC power storage means comprising: a unit battery composed of a single cell or a plurality of battery cells connected in series; and a plurality of parallel-connected unit battery groups composed of a plurality of the unit batteries connected in series, said DC backup power supply system further comprising a control circuit incorporating: connection switchover means capable of optionally changing the number of parallel-connections of the unit battery groups so as to correspond to a backup capacity of loads and implementing series-connection of the unit batteries inside the respective unit battery groups; a charger for recharging the respective unit battery group with DC power; and an output circuit through which DC power is discharged from the respective unit battery group to the loads.
22. A DC backup power supply system according to claim 21, wherein the charger and the output circuit comprise a DCDC converter.
23. A DC backup power supply system according to claim 21, wherein the connection switchover means comprise a relay circuit, and series-connection of the unit batteries is controlled by the relay circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A display, comprising:
(a) a display panel having a plurality of pixels arranged in a matrix having M pixel rows and N pixel columns, M scan lines electrically coupled to M pixel rows, respectively, and N data lines electrically coupled to N pixel columns, respectively, wherein M and N are integers greater than one;
(b) P signal lines for providing P video signals, wherein P is an integer greater than one;
(c) P multiplexers, wherein each multiplexer has an input electrically coupled to a corresponding signal line for receiving a corresponding video signal therefrom, and K channels, each channel comprising a first switch and a second switch parallel-connected between the input and a corresponding data line, for selectively transmitting the video signals, to the corresponding data line, wherein K is an integer greater than one; and
(d) K pairs of control lines for providing K pairs of control signals, respectively, wherein each pair of control lines is respectively and electrically coupled to the first and second switches of a corresponding channel of each multiplexer for providing a corresponding pair of control signals for turning on or off the first and second switches thereof, thereby selectively transmitting the video signal to the corresponding data line, wherein each pair of control signals are configured such that a time turning off one of the first and second switches is earlier than that turning off the other of the first and second switches,
wherein each of each pair of control signals has a waveform defined by a low voltage, a high voltage, a rising edge from the low voltage to the high voltage at a rising time, and a falling edge from the high voltage to the low voltage at a falling time, in a period, wherein for each control signal, the rising time is the time turning on a corresponding switch, and the falling time is the time turning off the corresponding switch, and wherein for each control signal, the rising time is earlier than the falling time; and
wherein for each pair of control signals, the falling time of the second control signal is later than the falling time of the first control signal, and the rising time of the second control signal is one of same as the falling time of the first control signal, later than the rising time but earlier than the falling time of the first control signal, and earlier than the rising time of the first control signal.
2. The display of claim 1, wherein P*K=N.
3. The display of claim 1, wherein each of the first and second switches of each channel of each multiplexer has a channel width, wherein the channel width of the first switch is identical to or different from that of the second switch.
4. The display of claim 1, wherein each of the first and second switches of each channel of each multiplexer comprises a transistor having a gate, a source and a drain, wherein the gate, the source and the drain of the first switch are electrically coupled to the first control signal of the pair of control signals, the input of the multiplexer, and the corresponding data line, respectively, and wherein the gate, the source and the drain of the second switch are electrically coupled to the second control signal of the pair of control signals, the source of the first switch and the drain of the first switch, respectively.
5. A multiplexer circuit for a display panel, wherein the display panel has a plurality of pixels arranged in a matrix having M pixel rows and N pixel columns, M scan lines electrically coupled to M pixel rows, respectively, and N data lines electrically coupled to N pixel columns, respectively, wherein M and N are integers greater than one, comprising:
(a) P multiplexers, wherein each multiplexer has an input electrically coupled to a corresponding signal line for receiving a corresponding video signal therefrom, and K channels, each channel comprising a first switch and a second switch parallel-connected between the input and a corresponding data line, for selectively transmitting the video signal to the corresponding data line, wherein P and K are integers greater than one; and
(b) K pairs of control lines for providing K pairs of control signals, respectively, wherein each pair of control lines is respectively and electrically coupled to the first and second switches of a corresponding channel of each multiplexer for providing a corresponding pair of control signals for turning on or off the first and second switches thereof, thereby selectively transmitting the video signal to the corresponding data line, wherein each pair of control signals are configured such that a time turning off one of the first and second switches is earlier than that turning off the other of the first and second switches,
wherein each of each pair of control signals has a waveform defined by a low voltage, a high voltage, a rising edge from the low voltage to the high voltage at a rising time, and a falling edge from the high voltage to the low voltage at a falling time, in a period, wherein for each control signal, the rising time is the time turning on a corresponding switch, and the falling time is the time turning off the corresponding switch, and wherein for each control signal, the rising time is earlier than the falling time; and
wherein for each pair of control signals, the falling time of the second control signal is later than the falling time of the first control signal, and the rising time of the second control signal is one of same as the falling time of the first control signal, later than the rising time but earlier than the falling time of the first control signal, and earlier than the rising time of the first control signal.
6. The multiplexer circuit of claim 5, wherein each of the first and second switches of each channel of each multiplexer comprises a transistor having a gate, a source and a drain, wherein the gate, the source and the drain of the first switch are electrically coupled to the first control signal of the pair of control signals, the input of the multiplexer, and the corresponding data line, respectively, and wherein the gate, the source and the drain of the second switch are electrically coupled to the second control signal of the pair of control signals, the source of the first switch and the drain of the first switch, respectively.
7. A method for driving a display panel, wherein the display panel has a plurality of pixels arranged in a matrix having M pixel rows and N pixel columns, M scan lines electrically coupled to M pixel rows, respectively, and N data lines electrically coupled to N pixel columns, respectively, wherein M and N are integers greater than one, comprising the steps of:
(a) providing a multiplexer circuit comprising:
P multiplexers, wherein each multiplexer has an input electrically coupled to a corresponding signal line for receiving a corresponding video signal therefrom, and K channels, each channel comprising a first switch and a second switch parallel-connected between the input and a corresponding data line, for selectively transmitting the video signal line to the corresponding data line, wherein P and K are integers greater than one; and
K pairs of control lines, wherein each pair of control lines is respectively and electrically coupled to the first and second switches of a corresponding channel of each multiplexer; and
(b) applying K pairs of control signals to the K pairs of control lines, respectively, such that each pair of control signals is respectively and electrically coupled to the first and second switches of the corresponding channel of each multiplexer for turning on or off the first and second switches thereof, thereby selectively transmitting the video signal to the corresponding data line, wherein each pair of control signals are configured such that a time turning off one of the first and second switches is earlier than that turning off the other of the first and second switches,
wherein each of each pair of control signals has a waveform defined by a low voltage, a high voltage, a rising edge from the low voltage to the high voltage at a rising time, and a falling edge from the high voltage to the low voltage at a falling time, in a period, wherein for each control signal, the rising time is the time turning on a corresponding switch, and the falling time is the time turning off the corresponding switch, and wherein for each control signal, the rising time is earlier than the falling time; and
wherein for each pair of control signals, the falling time of the second control signal is later than the falling time of the first control signal, and the rising time of the second control signal is one of same as the falling time of the first control signal, later than the rising time but earlier than the falling time of the first control signal, and earlier than the rising time of the first control signal.
8. The method of claim 7, wherein each of the pair of control signals has a waveform defined by a low voltage, a high voltage, a rising edge from the low voltage to the high voltage at a rising time, and a falling edge from the high voltage to the low voltage at a falling time in a period, wherein for each control signal, the rising time is the time turning on a corresponding switch, and the falling time is the time turning off the corresponding switch, and wherein for each control signal, the rising time is earlier than the falling time.