1. A method for forming the semiconductor memory device comprising:
etching a predetermined depth of an exposed semiconductor substrate using a capping pattern formed on the semiconductor substrate and forming a device isolating layer to construct a semiconductor fin surrounded by the device isolating layer and the capping pattern;
forming a material pattern including a trench exposing the capping pattern and a portion of the device isolating layer, on the capping pattern and the device isolating layer;
etching the device isolating layer exposed by the trench to expose sides of the semiconductor fin;
sequentially forming a conformal tunneling insulating layer, a charge storage layer and a blocking insulating layer on the exposed sides of the semiconductor fin and the capping pattern; and
forming a gate electrode layer on the blocking insulating layer to fill the trench.
2. The method of claim 1, further comprising performing an etch back process to leave the charge storage layer only on sides of the semiconductor fin after the forming of the charge storage layer before the forming of the blocking insulating layer.
3. The method of claim 1, further comprising removing the capping pattern exposed by the trench to expose the top surface of the semiconductor fin after the forming of the material pattern including the trench.
4. The method of claim 2, further comprising removing the capping pattern exposed by the trench to expose the top surface of the semiconductor fin after the forming of the material pattern including the trench.
5. The method of claim 3, wherein the charge storage layer is formed of at least one of nano-crystal, quantum dot, silicon, silicon-germanium, a metal layer and a nitride layer.
6. The method of claim 3, further comprising performing a thermal oxidation process or a thermal treatment process in a hydrogen ambient to round a sharp edge of the semiconductor fin after exposing sides of the semiconductor fin or the top surface and sides of the semiconductor fin and before the forming of the tunneling insulating layer.
7. The method of claim 3, further comprising performing an ion implantation process for forming a channel after exposing the sides of the semiconductor fin or the top surface and the sides of the semiconductor fin.
8. The method of claim 3, wherein the forming of the material pattern including a trench exposing the capping pattern and a portion of the device isolating layer, on the capping pattern and the device isolating layer comprises:
forming a buffer layer and a material layer on the capping pattern and the device isolating layer; and
patterning the material layer and the buffer oxide layer successively.
9. The method of claim 3, further comprising patterning the gate electrode layer to leave only on the sides of the semiconductor fin.
10. The method of claim 3, wherein the semiconductor substrate includes an SOI substrate, a GOI substrate, an SGOI substrate, and a strained silicon substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A PWM signal generating circuit, comprising:
a single counter configured to count values expressed in N bits; and
at least one arithmetic device configured to generate a PWM signal, each of the at least one arithmetic device including:
a pulse width data storage unit for storing N-bit pulse width data representing a pulse width of the PWM signal to be generated; and
an adder for calculating a carry value from a most significant bit obtained when adding the count value and the pulse width data,
wherein a signal having a level corresponding to the carry value is output at every change in the count value so that the PWM signal having the pulse width of the pulse width data is generated.
2. The PWM signal generating circuit according to claim 1, wherein the adder does not calculate a sum of the count value and the pulse width data.
3. The PWM signal generating circuit according to claim 1, wherein the counter generates an enable bit indicating that count is performed, and
the adder uses the enable bit as a carry value to a least significant bit.
4. The PWM signal generating circuit according to claim 1, wherein the counter is an up counter.
5. The PWM signal generating circuit according to claim 1, wherein the counter is a down counter.
6. The PWM signal generating circuit according to claim 1, wherein the counter is an up-down counter.
7. The PWM signal generating circuit according to claim 6, wherein the counter counts only one of an even number value and an odd number value in the count values expressed in the N bits in an up-count operation and counts only the other in a down-count operation.
8. The PWM signal generating circuit according to claim 1, wherein, when the at least one of arithmetic device includes a plurality of arithmetic devices,
the pulse width data storage units of the plurality of arithmetic devices respectively store pulse width data representing different pulse widths, and
the arithmetic devices respectively generate the plurality of PWM signals having the different pulse widths.
9. A printer comprising:
a photoreceptor;
the PWM signal generating circuit according to claim 8;
a plurality of light sources configured to irradiate the photoreceptor in a predetermined light quantity; and
a plurality of driver circuits configured to drive the light sources,
wherein the plurality of PWM signals are input to the driver circuits respectively and control the light quantities of the light sources respectively.
10. A PWM signal generating method, performed by a PWM signal generating circuit including a single counter and at least one arithmetic device, the method comprising:
storing, in each of the at least one arithmetic device, N-bit pulse width data representing a pulse width of the PWM signal to be generated;
generating a count value expressed in N bits by using the counter; and
calculating a carry value from a most significant bit obtained when adding the count value and the pulse width data by using each of the at least one arithmetic device,
wherein a signal having a level corresponding to the carry value is output at every change in the count value so that the PWM signal having the pulse width of the pulse width data is generated.