1. A bias circuit comprising:
a regulator circuit having a first resistive element coupled to a first transistor, and control circuitry for biasing the first transistor such that a nominal quiescent current flows through the first resistive element; and
a current diverting circuit coupled in parallel with the first transistor, wherein the current diverting circuit is adapted to operate in a disabled state and an enabled state, wherein a first quiescent current flows through the first transistor and a first diverted current flows through the current diverting circuit in the disabled state, and a second quiescent current flows through the first transistor and a second diverted current flows through the current diverting circuit in the enabled state.
2. The bias circuit of claim 1, wherein the first diverted current is negligible, such that the first quiescent current is approximately equal to the nominal quiescent current.
3. The bias circuit of claim 1, wherein the second diverted current is larger than the first diverted current.
4. The bias circuit of claim 1, wherein the current diverting circuit comprises:
a switch circuit;
a switch control circuit coupled to the switch circuit; and
a current select circuit coupled in parallel with the first transistor through the switch circuit.
5. The bias circuit of claim 4, wherein the current select circuit is coupled to the control circuitry of the regulator circuit, such that the current select circuit and the first transistor are commonly biased.
6. The bias circuit of claim 5, wherein the current select circuit comprises a second transistor, wherein gates of the first and second transistors are commonly biased.
7. The bias circuit of claim 6, wherein the current select circuit further comprises a third transistor, wherein gates of the first, second and third transistors are commonly biased.
8. The bias circuit of claim 4, wherein the switch circuit comprises one or more transistors.
9. The bias circuit of claim 4, wherein the switch control circuit comprises an adjustable voltage source coupled to the switch circuit.
10. The bias circuit of claim 9, wherein the switch control circuit further comprises one or more level shifters coupling the adjustable voltage source to the switch circuit.
11. The bias circuit of claim 9, wherein the switch control circuit further comprises a voltage divider circuit coupling the adjustable voltage source to the switch circuit.
12. The bias circuit of claim 1, wherein the sum of the first quiescent current and the first diverted current is equal to the nominal quiescent current, and the sum of the second quiescent current and the second diverted current is equal to the nominal quiescent current.
13. A method of biasing a circuit, comprising:
biasing a first resistive element and a first transistor using a feedback configuration, such that a first quiescent current flows through the first resistive element and the first transistor in a disabled state;
diverting current from the first transistor, such that the first quiescent current continues to flow through the first resistive element, and a second quiescent current, less than the first quiescent current, flows through the first transistor in enabled state; and
biasing a circuit based on whether the first quiescent current or the second quiescent current is flowing through the first transistor.
14. The method of claim 13, further comprising diverting current from the first transistor, such that the first quiescent current continues to flow through the first resistive element, and a third quiescent current, less than the second quiescent current, flows through the first transistor in a third state.
15. The method of claim 13, wherein the step of diverting current comprises:
coupling a second transistor in parallel with the first transistor; and
commonly biasing the first and second transistors.
16. The method of claim 15, further comprising:
coupling a third transistor in parallel with the first and second transistors; and
commonly biasing the first, second and third transistors.
17. The method of claim 15, further comprising selecting relative sizes of the first and second transistors to select the first and second quiescent currents.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A thin-film semiconductor device comprising:
a first plurality of thin-film transistors having different driving voltages than a second plurality of thin-film transistors, wherein said first and second plurality of transistors are formed on a glass substrate,
wherein an electric field of a gate electrode at each of said driving voltages of said first and second plurality of thin-film transistors is in a range of about 1MVcm to 2MVcm, and a drain concentration of P-type thin-film transistors is in a range of about 3E19cm3 to 1E20cm3.
2. The thin-film semiconductor device according to claim 1,
wherein said first plurality of thin-film transistors comprising N-type and P-type thin-film transistors have a lower driving voltage than said second plurality of thin-film transistors comprising N-type and P-type thin film transistor.
3. The thin-film semiconductor device according to claim 1,
wherein a plurality of gate insulating films of said first and second plurality of thin-film transistors have substantially the same thickness.
4. The thin-film semiconductor device according to claim 2,
wherein at least one N-type thin-film transistor of said second plurality of thin-film transistors have a lightly-doped drain structure.
5. A thin-film semiconductor device comprising:
a first plurality of thin-film transistors having different driving voltages than a second plurality of thin-film transistors, wherein said first and second plurality of transistors are formed on a glass substrate,
wherein an electric field of a gate electrode at each of said driving voltages of said first and second plurality of thin-film transistors is in a range of about 0.2MVcm to 0.8MVcm, and a drain concentration of P-type thin-film transistors is in a range of about 3E19cm3 to 1E20cm3.
6. The thin-film semiconductor device according to claim 5,
wherein said first and second plurality of thin-film transistors comprising N-type and P-type thin-film transistors have a lower driving voltage than said second plurality of thin-film transistors comprising N-type and P-type thin film transistor.
7. The thin-film semiconductor device according to claim 5,
wherein a plurality of gate insulating films of said first and second plurality of thin-film transistors has substantially the same thickness.
8. The thin-film semiconductor device according to claim 6,
wherein at least one N-type thin-film transistor of said second plurality of thin-film transistors have a lightly-doped drain structure.
9. A thin-film semiconductor device comprising:
a first plurality of thin-film transistors having a driving voltage which is lower than a driving range of a second plurality of thin-film transistors, wherein said first and second plurality of thin-film transistors are formed on a glass substrate,
wherein a drain concentration of said first and second plurality of thin-film transistors is in a range of about 3E19cm3 to 1E20cm3.
10. The thin-film semiconductor device according to claim 9,
wherein a plurality of gate insulating films of said first and second plurality of thin-film transistors have substantially the same thickness.
11. The thin-film semiconductor device according to claim 9,
wherein said first and second plurality of thin-film transistors comprise N-type and P-type thin-film transistors.
12. The thin-film semiconductor device according to claim 9,
wherein gate insulating films of said first and second plurality of thin-film transistors are formed of substantially the same materials.
13. A liquid crystal display comprising:
a thin-film semiconductor device according to claim 1; and
a driver circuit.
14. A liquid crystal display comprising:
a thin-film semiconductor device according to claim 9; and
a driver circuit.
15. A thin-film semiconductor device manufacturing method comprising:
providing a glass substrate
forming a plurality of gate insulating films of a plurality of thin-film transistors, wherein said gate insulating films are formed so as to have a substantially the same thickness, and
wherein said plurality of thin-film transistors have different driving voltages.
16. The thin-film semiconductor device manufacturing method according to claim 15,
wherein said gate insulating films are formed at substantially the same time.
17. The thin-film semiconductor device manufacturing method according to claim 15, further comprising:
forming sourcedrain regions of a plurality of P-type thin-film transistors having different driving voltages.
18. The thin-film semiconductor device manufacturing method according to claim 15, further comprising:
forming sourcedrain regions of a plurality of N-type thin-film transistors having different driving voltages.
19. The thin-film semiconductor device manufacturing method according to claim 17,
wherein said sourcedrain regions are formed at substantially the same time.
20. The thin-film semiconductor device manufacturing method according to claim 18,
wherein said sourcedrain regions are formed at substantially the same time.
21. The thin-film semiconductor device manufacturing method according to claim 18, further comprising:
forming Lightly-doped drain structure on at least one part of the N-type thin-film transistors.