1. (canceled)
2. A data processing apparatus configured to map input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol into an output symbol stream, the data processing apparatus comprising:
an interleaver configured to read-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved onto the sub-carrier signals, and
an address generator configured to generate the set of addresses, an address being generated for each of the input for mapping the input data symbol onto one of the sub-carrier signals, the address generator comprising:
a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial,
a permutation circuit configured to receive the content of the shift register stages and to permute the order of the bits present in the register stages in accordance with a permutation code to form an address, and
a control unit configured in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein
the permutation circuit is configured to change the permutation code, which permutes the order of the bits of the register stages to form the set of addresses from one OFDM symbol to another.
3. The data processing apparatus as claimed in claim 2, wherein the permutation circuit is configured to cycle through a sequence of different permutation codes for successive OFDM symbols.
4. The data processing apparatus as claimed in claim 2, wherein the OFDM symbol includes pilot sub-carriers, which are configured to carry known symbols, and the predetermined maximum valid address depends on a number of the pilot sub-carrier symbols present in the OFDM symbol.
5. The data processing apparatus as claimed in claim 2, wherein the number of sub-carriers is determined by one of a plurality of operating modes, and when an operating mode provides a number of the sub-carriers which is half or less than half a maximum number of sub-carriers in the OFDM symbols of any of the operating modes, and the data symbols include first sets of input data symbols for mapping onto first OFDM symbols and second sets of input data symbols for mapping onto second OFDM symbols, the data processing apparatus is configured to interleave the first and second sets of data symbols into the output data stream in accordance with an odd interleaving process,
the odd interleaving process including:
writing the first sets of input data symbols received from the sub-carriers of the first OFDM symbols into a first part of the interleaver memory in accordance with a sequential order of the first sets of input data symbols,
reading out the first sets of input data symbols from the first part of the interleaver memory into the output data stream in accordance with an order defined by the sets of addresses generated with one of the permutation codes of the sequence,
writing the second set of input data symbols received from the sub-carriers of the second OFDM symbols into a second part of the interleaver memory in accordance with a sequential order of the second sets of input data symbols.
reading out the second sets of input data symbols from the second part of the interleaver memory into the output data stream in accordance with an order defined by the sets of addresses generated with another of the permutation codes of the sequence.
6. The data processing apparatus according to claim 2 wherein the permutation code defines for respective register stages, the position to which the content of the register stage is sent and wherein in one of the operating modes a permutation code is defined in the following table:
Register Stage
10
9
8
7
6
5
4
3
2
1
0
Position
7
10
5
8
1
2
4
9
0
3
6
7. The data processing apparatus according to claim 2 wherein the permutation code defines for respective register stages, the position to which the content of the register stage is sent and wherein in one operating mode a permutation code is defined in the following table:
Register Stage
12
11
10
9
8
7
6
5
4
3
2
1
0
Position
8
4
3
2
0
11
1
5
12
10
6
7
9
and the permutation circuit is configured to change the permutation code to another defined in the following table:
Register Stage
12
11
10
9
8
7
6
5
4
3
2
1
0
Position
7
9
5
3
11
1
4
0
2
12
10
8
6
8. A transmitter for transmitting data using Orthogonal Frequency Division Multiplexing (OFDM) the transmitter including a data processing apparatus configured to map the input data symbols onto a predetermined number of sub-carrier signals of OFDM symbols, the data processing apparatus comprising:
an interleaver configured to read-into a memory the predetermined number of data for mapping onto the OFDM sub-carrier symbols, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved onto the sub-carrier signals, and
an address generator configured to generate the set of addresses, an address being generated for each of the input data symbols for mapping onto one of the sub-carrier signals, the address generator comprising:
a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial,
a permutation circuit configured to receive the content of the shift register stages and to permute the order of the bits present in the register stages in accordance with a permutation code to form an address, and
a control unit configured in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein
the permutation circuit is configured to change the permutation code, which permutes the order of the bits of the register stages to form the set of addresses from one OFDM symbol to another.
9. The transmitter as claimed in claim 8, wherein the transmitter is configured to transmit data which has been modulated in accordance with a Digital Video Broadcasting standard including the Digital Video Broadcasting-Terrestrial standard, the Digital Video Broadcasting-Handheld, or the Digital Video Broadcasting-Terrestrial2 standard.
10. A method of mapping symbols to be communicated onto predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols, the method comprising:
reading-into a memory the predetermined number of data symbols from the OFDM sub-carrier signals,
reading-out of the memory the data symbols into the output symbol stream to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved onto the OFDM sub-carrier signals, and
generating the set of addresses, an address being generated for each of the input symbols for mapping the input data symbol onto one of the sub-carrier signals, the generating the set of addresses comprising:
using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial,
using a permutation circuit to receive the content of the shift register stages and to permute the order of the bits present in the register stages in accordance with a permutation code to form an address,
re-generating an address when a generated address exceeds a predetermined maximum valid address, and
changing, by the permutation circuit, the permutation code, which permutes the order of the bits of the register stages to form the set of addresses from one OFDM symbol to another.
11. The method as claimed in claim 10, wherein the changing the permutation code includes cycling through a sequence of different permutation codes for successive OFDM symbols.
12. The method as claimed in claim 10, wherein the OFDM symbol includes pilot sub-carriers, which are configured to carry known symbols, and the predetermined maximum valid address depends on a number of the pilot sub-carrier symbols present in the OFDM symbol.
13. The method as claimed in claim 10, wherein the number of sub-carriers is determined by one of a plurality of operating modes, and when the and when operating mode provides a number of sub-carriers which is half or less than half a maximum number of sub-carriers in the OFDM symbols of any of the operating modes, and the data symbols include first sets of data symbols for mapping onto first OFDM symbols and second sets of data symbols for mapping onto second OFDM symbols, and the reading-into the memory the predetermined number of data symbols from the OFDM sub-carrier signals, and the reading-out of the memory the data symbols into the output symbol stream is in accordance with an odd interleaving process, the odd interleaving process including:
writing the first sets of input data symbols received from the sub-carriers of the first OFDM symbols into a first part of the interleaver memory in accordance with a sequential order of the first sets of input data symbols,
reading out the first sets of input data symbols from the first part of the interleaver memory into the output data stream in accordance with an order determined by the set of addresses generated with one of the permutation codes of the sequence,
writing the second set of input data symbols received from the sub-carriers of the second OFDM symbols into a second part of the interleaver memory in accordance with a sequential order of the second sets of input data symbols,
and reading out the second sets of input data symbols from the second part of the interleaver memory into the output data stream in accordance with an order defined by the set of addresses generated with another of the permutation codes of the sequence.
14. The method according to claim 10, wherein the permutation code defines for respective register stages, the position to which the content of the register stage is sent and wherein in one of the operating modes a permutation code is defined in the following table:
Register Stage
10
9
8
7
6
5
4
3
2
1
0
Position
7
10
5
8
1
2
4
9
0
3
6
15. The method according to claim 10, wherein the permutation code defines for respective register stages, the position to which the content of the register stage is sent and wherein in one operating mode a permutation code is defined in the following table:
Register Stage
12
11
10
9
8
7
6
5
4
3
2
1
0
Position
8
4
3
2
0
11
1
5
12
10
6
7
9
and wherein the method includes changing the permutation code to another defined in the following table:
Register Stage
12
11
10
9
8
7
6
5
4
3
2
1
0
Position
7
9
5
3
11
1
4
0
2
12
10
8
6
16. A receiver configured to de-interleave data received from a transmitter according to claim 8.
17. A receiver configured to de-interleave data interleaved according to the method of claim 10.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A do-it-yourself ceiling fan with a ceiling lamp having a ceiling frame in a switch box of a ceiling fan, and a guide head at a top of a ceiling lamp; the guide head being exactly inserted into the ceiling frame; wherein
a center of the ceiling frame has a through hole; a top thereof is vertically extended with a receptacle with an electric wire passing through the receptacle; the receptacle is exactly coupled to the through hole at a center of the ceiling frame; two sides of the ceiling frame have lateral holes; the through hole communicates the two lateral holes; a lower end of the ceiling frame is horizontally extended with a supporting plate and a confining structure is installed above the supporting plate;
the confining structure is formed by a hollow cylinder seat above the supporting plate, a control rod passing through the cylinder seat; a spring installed to the control rod; a confining inserting rod locked to a front of the control rod; a buckling block is protruded from a middle section of the control rod; a front end of the control rod has a threaded section; the control rod passes through the cylinder seat and the spring; then the control rod is locked to a distal end of the confining inserting rod so as to confine the spring to an interior of the cylinder seat and the confining inserting rod is pulled at the same time; a distal end of the cylinder seat is installed with a notch for being inserted by the buckling block of the control rod; a front section of the confining inserting rod is a forked rod which are extended to two lateral holes at two sides of the ceiling frame and meanwhile resists against the lateral wings of the guide head for preventing the guide head from falling down; the confining inserting rod has a resisting ring coupled to a distal end of the control rod; the resisting ring exactly resists against the lateral side of the spring; thereby, when the confining inserting rod pulls backwards with the control rod, the resisting ring exactly compresses the spring so that the confining inserting rod is separated from the guide head;
a lower end of the guide head passes through the ceiling lamp in advance; a lateral side of the guide head has lateral wings with respect to the lateral holes and capable of inserting into the lateral holes; the confining inserting rod is installed between the two lateral holes; the confining inserting rod is inserted into the inserting space; after the guide head is inserted into the ceiling frame; a plug at a top thereof exactly inserts into the receptacle; and
thereby, a user can assemble the ceiling fan with the ceiling lamp by himself or herself for reducing a storage volume.
2. The do-it-yourself ceiling fan with a ceiling lamp as claimed in claim 1, wherein a buckling block is protruded from a middle section of the control rod; a distal end of the cylinder seat has a notch for being passed through by the buckling block so that the control rod can rotate and is positioned therein.
3. The do-it-yourself ceiling fan with a ceiling lamp as claimed in claim 1, wherein a lower end of the guide head has a threaded portion; the threaded portion passes through the ceiling lamp; a nut serves to lock the top end of the ceiling lamp.
4. The do-it-yourself ceiling fan with a ceiling lamp as claimed in claim 1, wherein a lateral side of the ceiling frame has an inserting hole; a lower side of the inserting hole is locked with a confining piece having a protruding portion which exactly inserts into the through hole so that the guide head is buckled therein; a side of the guide head coupled to the confining piece has an embedding groove; after the guide head inserts into a lower end of the ceiling frame, the embedding groove of the guide head exactly resists against the confining piece of the ceiling frame.