1. An electrical nonlinear pulse oscillator, comprising:
a nonlinear transmission line; and
a distributed nonlinear amplifier arrangement coupled to the nonlinear transmission line and arranged along a length of the nonlinear transmission line,
wherein the oscillator is configured to propagate along the nonlinear transmission line at least one nonlinear pulse.
2. The oscillator of claim 1, wherein the at least one nonlinear pulse significantly resembles a soliton waveform.
3. The oscillator of claim 1, wherein the at least one nonlinear pulse includes a cnoidal wave.
4. The oscillator of claim 1, wherein the nonlinear transmission line includes a coplanar waveguide.
5. The oscillator of claim 4, wherein the nonlinear transmission line includes a plurality of Schottky diodes distributed along the coplanar waveguide.
6. The oscillator of claim 1, wherein the distributed nonlinear amplifier arrangement includes a plurality of resonant tunneling diodes.
7. The oscillator of claim 4, further comprising a feedback network coupled to the nonlinear transmission line and configured to control the plurality of resonant tunneling diodes so as to have an automatically adjustable nonlinear gain.
8. The oscillator of claim 7, wherein the feedback network is configured to control the plurality of resonant tunneling diodes to have a first gain greater than unity when the at least one nonlinear pulse has an amplitude at a monitored point that is less than a target amplitude and a second gain less than unity when the at least one nonlinear pulse has an amplitude at the monitored point that is greater than the target amplitude.
9. The oscillator of claim 8, wherein the feedback network includes an R-C network to perform a DC averaging of the at least one nonlinear pulse.
10. A phase locked loop comprising the oscillator of claim 1.
11. A method for generating periodic electrical nonlinear pulses, comprising acts of:
A) providing distributed amplification or attenuation to a first signal along a nonlinear transmission line; and
B) adjusting the distributed amplification or attenuation based on an average DC voltage of the first signal at a monitored point on the nonlinear transmission line, such that the first signal develops and maintains the periodic nonlinear pulses having a target amplitude at the monitored point.
12. The method of claim 11, wherein the act A) includes acts of amplifying the first signal when the average voltage of the first signal has a first value less than a value representing the target amplitude, and attenuating the first signal when the average value of the first signal has a second value greater than the value representing the target amplitude.
13. An electrical nonlinear pulse oscillator, comprising:
a first nonlinear transmission line;
a nonlinear amplifier coupled to the nonlinear transmission line in a closed loop arrangement; and
a two-port nonlinear transmission line coupled to the first nonlinear transmission line,
wherein the oscillator is configured to propagate along the first nonlinear transmission line at least one nonlinear pulse, and wherein the two-port nonlinear transmission line is configured to provide pulse compression to the at least one nonlinear pulse.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A liquid crystal display panel, comprising:
a color filter substrate;
a thin film transistor array substrate, disposed parallel to the color filter substrate, wherein the thin film transistor array substrate has a plurality of gate layer lines and a plurality of source layer lines thereon;
a plurality of spacers, disposed on the color filter substrate, wherein the spacers at least lean on one of the side edges of the gate layer lines or the source layer lines, and the spacers are disposed at the overlapping area between the gate layer lines and the source layer lines with the spacers leaning against both the gate layer lines and the source layer lines, wherein adjacent spacers are joined together on the color filter substrate to form a latching structure such that a central recess section of the latching structure is able to latch onto the overlapping area between the gate layer lines and the source layer lines; and
a liquid crystal layer, disposed between the color filter substrate and the thin film transistor array substrate.
2. The liquid crystal display panel of claim 1, wherein the gate layer lines comprise scan lines and the source layer lines comprise data lines.
3. The liquid crystal display panel of claim 2, wherein the gate layer lines further comprise common lines.
4. The liquid crystal display panel of claim 1, wherein the spacers have a cylindrical or a wall-like shape.
5. A liquid crystal display panel, comprising:
a color filter substrate;
a thin film transistor array substrate, disposed parallel to the color filter substrate, wherein the thin film transistor array substrate has a plurality of gate layer lines and a plurality of source layer lines thereon;
a plurality of spacers, disposed on the color filter substrate, wherein the spacers at least lean on one of the side edges of the gate layer lines or the source layer lines, and the spacers are disposed on opposite sides of the gate layer lines with the spacers leaning against the gate layer lines as well, wherein adjacent spacers are joined together on the color filter substrate to form a latching structure such that a central recess section of the latching structure is able to latch onto the gate layer lines; and
a liquid crystal layer, disposed between the color filter substrate and the thin film transistor array substrate.
6. The liquid crystal display panel of claim 5, wherein the gate layer lines comprise scan lines and the source layer lines comprise data lines.
7. The liquid crystal display panel of claim 6, wherein the gate layer lines further comprise common lines.
8. The liquid crystal display panel of claim 5, wherein the spacers have a cylindrical or a wall-like shape.
9. A liquid crystal display panel, comprising:
a color filter substrate;
a thin film transistor array substrate, disposed parallel to the color filter substrate, wherein the thin film transistor array substrate has a plurality of gate layer lines and a plurality of source layer lines thereon;
a plurality of spacers, disposed on the color filter substrate, wherein the spacers at least lean on one of the side edges of the gate layer lines or the source layer lines, and the spacers are disposed on opposite sides of the source layer lines with the spacers leaning against the source layers as well, wherein adjacent spacers are joined together on the color filter substrate to form a latching structure such that a central recess section of the latching structure is able to latch onto the source layers; and
a liquid crystal layer, disposed between the color filter substrate and the thin film transistor array substrate.
10. The liquid crystal display panel of claim 9, wherein the gate layer lines comprise scan lines and the source layer lines comprise data lines.
11. The liquid crystal display panel of claim 10, wherein the gate layer lines further comprise common lines.
12. The liquid crystal display panel of claim 9, wherein the spacers have a cylindrical or a wall-like shape.