What is claimed is:
1. A light-emitting panel comprising:
a first substrate, wherein the first substrate comprises a plurality of sockets;
a plurality of micro-components, wherein each micro-component comprises a shell at least partially filled with a plasma-forming gas and wherein at least one micro-component of the plurality of micro-components is at least partially disposed in each socket;
a second substrate, wherein the second substrate is opposed to the first substrate such that the at least one micro-component is sandwiched between the first substrate and the second substrate; and
a plurality of electrodes, wherein at least two electrodes of the plurality of electrodes are adhered to only the first substrate, only the second substrate, or at least one electrode is adhered to each of the first substrate and the second substrate and wherein the at least two electrodes are arranged so that voltage supplied to the at least two electrodes causes one or more micro-components to emit radiation.
2. The light-emitting panel of claim 1, wherein the second substrate comprises at least one lens.
3. The light-emitting panel of claim 2, wherein the at least one lens is configurable to adjust a field of view of the light-emitting panel.
4. The light-emitting panel of claim 1, wherein the second substrate comprises at least one filter.
5. The light-emitting panel of claim 4, wherein the plurality of micro-components are configured to emit ultraviolet radiation, wherein each micro-component is coated with phosphor to convert the ultraviolet radiation to visible light, and wherein the at least one filter changes the visible light passing through the filter to visible light of a specific color.
6. A light-emitting panel, comprising:
a first substrate, wherein the first substrate comprises a plurality of sockets;
a plurality of micro-components, wherein each micro-component comprises a shell at least partially filled with a plasma-forming gas and wherein at least one micro-component of the plurality of micro-components is at least partially disposed in each socket;
a second substrate, wherein the second substrate is opposed to the first substrate such that the at least one micro-component is sandwiched between the first substrate and the second substrate; and
a plurality of electrodes, wherein at least two electrodes of the plurality of electrodes are arranged so that voltage supplied to the at least two electrodes causes one or more micro-components to emit radiation throughout the field of view of the light-emitting panel without crossing the at least two electrodes.
7. The light-emitting panel of claim 6, wherein the first substrate dissipates heat from the light-emitting panel.
8. A light-emitting panel comprising:
a first substrate, wherein the first substrate comprises a plurality of sockets and wherein each socket comprises at least one enhancement material;
a plurality of micro-components, wherein each micro-component comprises a shell at least partially filled with a plasma-forming gas and wherein at least one micro-component of the plurality of micro-components is at least partially disposed in each socket;
a second substrate, wherein the second substrate is opposed to the first substrate such that the at least one micro-component is sandwiched between the first substrate and the second substrate; and
a plurality of electrodes, wherein at least two electrodes of the plurality of electrodes are arranged so that voltage supplied to the at least two electrodes causes one or more micro-components to emit radiation.
9. The light-emitting display of claim 8, wherein the at least one enhancement material is disposed in or proximate to each socket and wherein the at least one enhancement material is selected from a group consisting of transistors, integrated-circuits, semiconductor devices, inductors, capacitors, resistors, control electronics, drive electronics, diodes, pulse-forming networks, pulse compressors, pulse transformers, and tuned-circuits.
10. The light-emitting display of claim 9, wherein the at least one enhancement material self-aligns in each socket.
11. The light-emitting display of claim 9, further comprising a controller, wherein the controller selectively controls the operation of the at least one enhancement material to adjust at least one characteristic of the micro-component.
12. A curing or sterilization device comprising a light-emitting panel, wherein the light-emitting panel comprises:
a first substrate, wherein the first substrate comprises a plurality of sockets;
a plurality of micro-components, wherein each micro-component comprises a shell at least partially filled with a plasma-forming gas, wherein the micro-component is configured to emit ultraviolet light, and wherein at least one micro-component of the plurality of micro-components is at least partially disposed in each socket;
a second substrate, wherein the second substrate is opposed to the first substrate such that the at least one micro-component is sandwiched between the first substrate and the second substrate; and
a plurality of electrodes, wherein at least two electrodes of the plurality of electrodes are arranged so that voltage supplied to the at least two electrodes causes one or more micro-components to emit the ultraviolet light.
13. The curing or sterilization device of claim 12, wherein the at least two electrodes of the plurality of electrodes are adhered to only the first substrate, only the second substrate, or at least one electrode is adhered to each of the first substrate and the second substrate.
14. The curing or sterilization device of claim 12, wherein the ultraviolet light is emitted throughout the field of view of the light-emitting panel without crossing the at least two electrodes.
15. A high resolution light-emitting panel, comprising:
a first substrate, wherein the first substrate comprises a plurality of sockets;
a plurality of micro-components, wherein each micro-component comprises a shell at least partially filled with a plasma-forming gas, wherein the micro-component is configured to emit radiation, and wherein at least one micro-component of the plurality of micro-components is at least partially disposed in each socket;
a second substrate, wherein the second substrate is opposed to the first substrate such that the at least one micro-component is sandwiched between the first substrate and the second substrate; and
a plurality of electrodes, wherein at least two electrodes of the plurality of electrodes are arranged so that voltage supplied to the at least two electrodes causes one or more micro-components to emit radiation.
16. A web fabrication process for manufacturing a plurality of light-emitting panels, the process comprising the steps of:
providing a first substrate;
disposing a plurality of micro-components on the first substrate;
disposing a second substrate over the first substrate such that the plurality of micro-components are sandwiched between the first substrate and the second substrate; and
dicing the first substrate and the second substrate to form individual light-emitting panels.
17. The process of claim 16, wherein the first substrate, the second substrate or the first substrate and the second substrate are provided as rolls of material.
18. The process of claim 16, wherein the first substrate comprises a plurality of sockets.
19. The process of claim 16, further comprising the step of disposing at least two electrodes on the first substrate, the second substrate, or at least one electrode on each of the first substrate and the second substrate.
20. The process of claim 19, wherein each light-emitting panel comprises the at least two electrodes, wherein the at least two electrodes are adhered to only the first substrate, only the second substrate, or at least one electrode is adhered to each of the first substrate and the second substrate, and wherein the at least two electrodes are arranged so that voltage supplied to the at least two electrodes causes one or more micro-components to emit radiation.
21. The process of claim 19, wherein each light-emitting panel comprises the at least two electrodes and wherein the two electrodes are arranged so that voltage supplied to the at least two electrodes causes one or more micro-components to emit radiation throughout the field of view of the individual light-emitting panel without crossing the at least two electrodes.
22. The process of claim 16, further comprising the steps of forming a plurality of sockets in the first substrate and wherein the step of disposing a plurality of micro-components on the first substrate further comprises at least partially disposing at least one micro-component of the plurality of micro-components in each socket of the plurality of sockets.
23. The process of claim 22, wherein the first substrate comprises a plurality of material layers and wherein the step of forming a plurality of sockets in the first substrate comprises the steps of selectively removing a plurality of portions of the material layers to form a plurality of cavities.
24. The process of claim 22, wherein the step of forming a plurality of sockets in the first substrate comprises the steps of patterning the first substrate with a plurality of cavities.
25. The process of claim 24, further comprising the steps of disposing at least one material layer on the first substrate so that the at least one material layer conforms to the shape of each socket of the plurality of sockets and disposing at least one electrode between the first substrate and the at least one material layer.
26. The process of claim 24, further comprising the steps of disposing a plurality of material layers on the first substrate so that the plurality of material layers conform to the shape of each socket of the plurality of sockets and disposing at least one electrode within the plurality of material layers.
27. The process of claim 22, wherein the step of providing a first substrate comprises the step of forming a first substrate by disposing a plurality of material layers and wherein the step of forming a plurality of sockets in the first substrate further comprises the step of selectively removing a plurality of portions of the material layers to form a plurality of cavities.
28. The process of claim 27, further comprising the step of disposing at least one electrode on the first substrate, the second substrate, or the first substrate and the second substrate.
29. The process of claim 28, wherein the at least one electrode is sandwiched between two material layers of the plurality of material layers.
30. The process of claim 16, further comprising the step of disposing at least one enhancement material in, or proximate to, each socket.
31. The process of claim 30, wherein the at least on enhancement material is selected from a group consisting of transistors, integrated-circuits, semiconductor devices, inductors, capacitors, resistors, control electronics, drive electronics, diodes, pulse-forming networks, pulse compressors, pulse transformers, and tuned-circuits.
32. The process of claim 31, wherein the step of disposing the at least one enhancement material in or proximate to each socket comprises the steps of:
suspending the at least one enhancement material in liquid; and
flowing the liquid over the first substrate such that the at least one enhancement material settles in each socket.
33. The process of claim 31, wherein the sockets are of a corresponding shape to the at least one enhancement material and wherein the at least one enhancement material self-aligns in each socket.
34. The process of claim 16, further comprising the step of disposing a plurality of control electronics or drive electronics on the first substrate, the second substrate, or the first substrate and the second substrate.
35. The process of claim 16, wherein the web fabrication process is performed as a continuous high-speed inline process.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory comprising:
a plurality of memory cell blocks each including a plurality of memory cells;
a refresh control circuit for performing a read operation and a rewrite operation with respect to said memory cells;
a first count detection circuit for detecting an access frequency with respect to said memory cells;
a second count detection circuit for detecting an access frequency of each said memory cell block; and
a third count detection circuit detecting a frequency in which the sum of access frequencies of each said memory cell block counted by said second count detection circuit has not reached a prescribed frequency when said first count detection circuit detects that the sum of access frequencies with respect to said memory cells reaches a prescribed frequency.
2. The memory according to claim 1, wherein
said refresh control circuit performs a first refresh operation including a first read operation and a first rewrite operation with respect to said memory cells included in at least one of said memory cell blocks when the sum of frequencies counted by said third count detection circuit reaches a prescribed frequency.
3. The memory according to claim 2, wherein
when said first refresh operation is performed with respect to said memory cells, data having an opposite polarity to data held in said memory cells is written in said memory cells, and thereafter rewritten to said data held in said memory cells.
4. The memory according to claim 2, wherein
a first voltage pulse giving an electric field in a first direction and a second voltage pulse giving an electric field in a second direction opposite to said first direction are applied to selected said memory cell by the same number of times in said first refresh operation respectively.
5. The memory according to claim 2, wherein
said refresh control circuit performs a second refresh operation including a second read operation and a second rewrite operation with respect to said memory cells included in at least one of said memory cell blocks when the sum of frequencies counted by said second count detection circuit reaches a prescribed frequency, in addition to said first refresh operation.
6. The memory according to claim 2, wherein
said first refresh operation is a refresh operation for preventing an imprint, and
said first refresh operation further includes an additional cycle in which a voltage pulse having the same value as and an opposite polarity to a voltage pulse applied to said selected memory cell is applied to said selected memory cell in said first read operation.
7. The memory according to claim 6, wherein
said first rewrite operation includes a first rewrite and a second rewrite in which voltage pulses opposite to each other in polarity are applied to said selected memory cell.
8. The memory according to claim 7, wherein
said selected memory cell stores first data or second data, and
in a case where said first data is stored in said selected memory cell, said first data is rewritten in said additional cycle after said second data different from said first data is written in said first read operation, and thereafter said first rewrite and said second rewrite are performed at a voltage pulse not destroying said first data.
9. The memory according to claim 7, wherein
said selected memory cell stores first data or second data, and
in a case where said second data is stored in said selected memory cell, said first data is written in said additional cycle after said second data is rewritten in said first read operation, and thereafter said second data is rewritten in said second rewrite after said first data is rewritten in said first rewrite.
10. The memory according to claim 5, wherein
said second refresh operation is a refresh operation for preventing a disturbance,
said second rewrite operation of said second refresh operation includes a third rewrite and a fourth rewrite, and
voltages opposite to each other in polarity are applied to nonselected said memory cells in said third rewrite and said fourth rewrite respectively.
11. The memory according to claim 10, wherein no voltage pulse is applied to said nonselected memory cells in said second read operation of said second refresh operation.
12. The memory according to claim 2, wherein
said third count detection circuit is used as a counting circuit of a no-access frequency resulting in an imprint.
13. The memory according to claim 12, wherein
said refresh control circuit includes an imprint preventioncontrol circuit preventing said imprint by controlling said first refresh operation.
14. The memory according to claim 13, wherein
said imprint preventioncontrol circuit has a function of counting up said third count detection circuit of said memory cell block in which said second count detection circuit does not reach a prescribed access frequency and outputting a signal requesting said first refresh operation in a case where said third count detection circuit reaches a prescribed access frequency.
15. The memory according to claim 5, wherein
said first count detection circuit and said second count detection circuit are used as a counting circuit of an access frequency resulting in a disturbance.
16. The memory according to claim 15, wherein
said refresh control circuit includes a disturbance preventioncontrol circuit preventing said disturbance by controlling said second refresh operation.
17. The memory according to claim 16, wherein
said disturbance preventioncontrol circuit has a function of counting up said second count detection circuit and outputting a signal requesting said second refresh operation in a case where said second count detection circuit reaches a prescribed access frequency when said first count detection circuit reaches a prescribed access frequency.