1. A cell library, comprising:
one or more cells having one or more virtual buses, the one or more cells for an integrated circuit design, wherein the one or more virtual buses comprise:
a plurality of ports representing a common power signal, the plurality of ports including at least two power ports on a same layer, the at least two power ports separated by substantially insulating material in the same layer.
2. The library of claim 1, wherein the common power signal includes a fixed voltage signal.
3. The library of claim 1, wherein, after the at least two power ports are coupled together by one or more electrical paths, the plurality of ports representing the common power signal share the common power signal.
4. The library of claim 1, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
5. The library of claim 1, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
6. The library of claim 1, wherein an integrated circuit of the integrated circuit is formed by a Bipolar process.
7. The library of claim 1, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
8. The library of claim 1, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
9. The library of claim 1, wherein the one or more cells includes at least one standard cell.
10. The library of claim 1, wherein the one or more cells includes at least one gate array cell.
11. The library of claim 1, wherein the one or more cells includes at least one analog cell.
12. The library of claim 1, wherein the one or more cells includes at least one analog mixed signal cell.
13. The library of claim 1, wherein the one or more cells includes at least one analog and digital cell.
14 The library of claim 1, wherein the one or more cells includes at least one functional block cell.
15. A cell library, comprising:
one or more cells having one or more virtual buses, the one or more cells for an integrated circuit design, wherein the one or more virtual buses comprise:
a plurality of ports sharing a common power signal, the plurality of ports including at least two power ports on a same layer, the at least two power ports separated by substantially insulating material in the same layer, the at least two power ports coupled together via one or more electrical paths on one or more layers of metal.
16. The library of claim 15, wherein the common power signal includes a fixed voltage signal.
17. The library of claim 15, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
18. The library of claim 15, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
19. The library of claim 15, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
20. The library of claim 15, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
21. The library of claim 15, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
22. The library of claim 15, wherein the one or more cells includes at least one standard cell.
23. The library of claim 15, wherein the one or more cells includes at least one gate array cell.
24. The library of claim 15, wherein the one or more cells includes at least one analog cell.
25. The library of claim 15, wherein the one or more cells includes at least one analog mixed signal cell.
26. The library of claim 15, wherein the one or more cells includes at least one analog and digital cell.
27. The library of claim 15, wherein the one or more cells includes at least one functional block cell.
28. A cell library, comprising:
one or more virtual tap cells for an integrated circuit design, comprising:
one or more electrical couplings to at least one of: one or more wells and one or more substrates,
wherein at least one electrical coupling of the one or more electrical couplings is positioned entirely outside one or more hierarchies of the one or more virtual tap cells.
29. The library of claim 28, wherein the at least one of the one or more taps is placed physically entirely in one of the one or more virtual tap cells.
30. The library of claim 28, wherein the at least one of the one or more taps is placed physically partly in one of the one or more virtual tap cells.
31. The library of claim 28, wherein the at least one of the one or more taps is placed physically partly in one of the one or more other cells.
32. The library of claim 28, wherein the at least one electrical coupling is positioned physically on top of the one or more virtual tap cells.
33. The library of claim 28, wherein the at least one electrical coupling is positioned physically between at least two of the one or more virtual tap cells.
34. The library of claim 28, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
35. The library of claim 28, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
36. The library of claim 28, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
37. The library of claim 28, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
38. The library of claim 28, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
39. The library of claim 28, wherein the one or more cells includes at least one standard cell.
40. The library of claim 28, wherein the one or more cells includes at least one gate array cell.
41. The library of claim 28, wherein the one or more cells includes at least one analog cell.
42. The library of claim 28, wherein the one or more cells includes at least one analog mixed signal cell.
43. The library of claim 28, wherein the one or more cells includes at least one analog and digital cell.
44. The library of claim 28, wherein the one or more cells includes at least one functional block cell.
45. A cell library, comprising:
one or more cells for an integrated circuit design adapted to have a software tool perform placement of one or more features of the integrated circuit design, the placement of at least one of the one or more features occurring primarily to place one or more electrical couplings to one or more wells.
46. The library of claim 45, wherein the software tool includes a router.
47. The library of claim 45, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
48. The library of claim 45, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
49. The library of claim 45, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
50. The library of claim 45, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
51. The library of claim 45, wherein an integrated circuit of the integrated circuit design is formed by a Silicon on Insulator process.
52. The library of claim 45, wherein the one or more cells includes at least one standard cell.
53. The library of claim 45, wherein the one or more cells includes at least one gate array cell.
54. The library of claim 45, wherein the one or more cells includes at least one analog cell.
55. The library of claim 45, wherein the one or more cells includes at least one analog mixed signal cell.
56. The library of claim 45, wherein the one or more cells includes at least one analog and digital cell.
57. The library of claim 45, wherein the one or more cells includes at least one functional block cell.
58. A cell library, comprising:
one or more cells for an integrated circuit design adapted to have a software tool perform placement of one or more features of the integrated circuit design, the placement of at least one of the one or more features occurring at a granularity level of one or more electrical couplings to one or more wells.
59. The library of claim 58, wherein the software tool includes a router.
60. The library of claim 58, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
61. The library of claim 58, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
62. The library of claim 58, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
63. The library of claim 58, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
64. The library of claim 58, wherein an integrated circuit of the integrated circuit design is formed by a Silicon on Insulator process.
65. The library of claim 58, wherein the one or more cells includes at least one standard cell.
66. The library of claim 58, wherein the one or more cells includes at least one gate array cell.
67. The library of claim 58, wherein the one or more cells includes at least one analog cell.
68. The library of claim 58, wherein the one or more cells includes at least one analog mixed signal cell.
69. The library of claim 58, wherein the one or more cells includes at least one analog and digital cell.
70. The library of claim 58, wherein the one or more cells includes at least one functional block cell.
71. A cell library, comprising:
one or more cells for an integrated circuit design adapted to have a software tool perform placement of one or more features of the integrated circuit design, the placement of at least one of the one or more features occurring primarily to place one or more electrical couplings to one or more substrates.
72. The library of claim of 71, wherein the software tool includes a router.
73. The library of claim 71, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
74. The library of claim 71, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
75. The library of claim 71, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
76. The library of claim 71, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
77. The library of claim 71, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
78. The library of claim 71, wherein the one or more cells includes at least one standard cell.
79. The library of claim 71, wherein the one or more cells includes at least one gate array cell.
80. The library of claim 71, wherein the one or more cells includes at least one analog cell.
81. The library of claim 71, wherein the one or more cells includes at least one analog mixed signal cell.
82. The library of claim 71, wherein the one or more cells includes at least one analog and digital cell.
83. The library of claim 71, wherein the one or more cells includes at least one functional block cell.
84. A cell library, comprising:
one or more cells for an integrated circuit design adapted to have a software tool perform placement of one or more features of the integrated circuit design, the placement of at least one of the one or more features occurring at a granularity level of one or more electrical couplings to one or more substrates.
85. The library of claim 84, wherein the software tool includes a router.
86. The library of claim 84, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
87. The library of claim 84, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
88. The library of claim 84, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
89. The library of claim 84, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
90. The library of claim 84, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
91. The library of claim 84, wherein the one or more cells includes at least one standard cell.
92. The library of claim 84, wherein the one or more cells includes at least one gate array cell.
93. The library of claim 84, wherein the one or more cells includes at least one analog cell.
94. The library of claim 84, wherein the one or more cells includes at least one analog mixed signal cell.
95. The library of claim 84, wherein the one or more cells includes at least one analog and digital cell.
96. The library of claim 84, wherein the one or more cells includes at least one functional block cell.
97. A cell library, comprising:
one or more cells for an integrated circuit design, the one or more cells having one or more ports, the one or more ports adapted to couple to one or more metal substantially octagonal via structures.
98. The library of claim 97, wherein the one or more substantially octagonal via structures comprises a square via cut.
99. The library of claim 97, wherein the one or more substantially octagonal via structures comprises a rectangular via cut.
100. The library of claim 97, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
101. The library of claim 97, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
102. The library of claim 97, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
103. The library of claim 97, wherein an integrated circuit of the integrated circuit design is formed by a Gallium Arsenide process.
104. The library of claim 97, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
105. The library of claim 97, wherein the one or more cells includes at least one standard cell.
106. The library of claim 97, wherein the one or more cells includes at least one gate array cell.
107. The library of claim 97, wherein the one or more cells includes at least one analog cell.
108. The library of claim 97, wherein the one or more cells includes at least one analog mixed signal cell.
109. The library of claim 97, wherein the one or more cells includes at least one analog and digital cell.
110. The library of claim 97, wherein the one or more cells includes at least one functional block cell.
111. A cell library, comprising:
one or more cells for an integrated circuit design, comprising significant features including at least one of: signal ports, power ports, and one or more boundaries of the one or more cells,
wherein the significant features are freely placed according to a minimum drawing resolution.
112. The library of claim 111, wherein the minimum drawing resolution corresponds to a layout grid.
113. The library of claim 111, wherein the significant features include signal ports.
114. The library of claim 111, wherein the significant features include power ports.
115. The library of claim 111, wherein the significant features include one or more boundaries of the one or more cells.
116. The library of claim 111, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
117. The library of claim 111, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
118. The library of claim 111, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
119. The library of claim 111, wherein an integrated circuit i of the integrated circuit design is formed by a Gallium-Arsenide process.
120. The library of claim 111, wherein an integrated circuit i of the integrated circuit design s formed by a Silicon-on-Insulator process.
121. The library of claim 111, wherein the one or more cells includes at least one standard cell.
122. The library of claim 111, wherein the one or more cells includes at least one gate array cell.
123. The library of claim 111, wherein the one or more cells includes at least one analog cell.
124. The library of claim 111, wherein the one or more cells includes at least one analog mixed signal cell.
125. The library of claim 111, wherein the one or more cells includes at least one analog and digital cell.
126. The library of claim 111, wherein the one or more cells includes at least one functional block cell.
127. A cell library, comprising:
one or more arbitrarily shaped cells for an integrated circuit design, wherein the boundary of the arbitrarily shaped cells include vertices, the vertices adapted to be freely placed according to a minimum drawing resolution.
128. The library of claim 127, wherein the minimum drawing resolution corresponds to a layout grid.
129. The library of claim 127, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
130. The library of claim 127, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
131. The library of claim 127, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
132. The library of claim 127, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
133. The library of claim 127, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
134. The library of claim 127, wherein the one or more cells includes at least one standard cell.
135. The library of claim 127, wherein the one or more cells includes at least one gate array cell.
136. The library of claim 127, wherein the one or more cells includes at least one analog cell.
137. The library of claim 127, wherein the one or more cells includes at least one analog mixed signal cell.
138. The library of claim 127, wherein the one or more cells includes at least one analog and digital cell.
139. The library of claim 127, wherein the one or more cells includes at least one functional block cell.
140. A cell library, comprising:
one or more cells for an integrated circuit design, at least one of the one or more cells including at least one of: one or more standard cells, and one or more gate array cells,
wherein the one or more cells are designed to be substantially coupled by one or more routing wires freely placed according to a minimum drawing resolution.
141. The library of claim 140, wherein the minimum drawing resolution corresponds to a layout grid.
142. The library of claim 140, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
143. The library of claim 140, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
144. The library of claim 140, wherein the integrated circuit of the integrated circuit design is formed by a Bipolar process.
145. The library of claim 140, wherein the integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
146. The library of claim 140, wherein the integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
147. The library of claim 140, wherein the one or more cells includes at least one standard cell.
148. The library of claim 140, wherein the one or more cells includes at least one gate array cell.
149. A cell library, comprising:
one or more cells for an integrated circuit design, the one or more cells having one or more ports clipped by an angle.
150. The library of claim 149, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
151. The library of claim 149, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
152. The library of claim 149, wherein the integrated circuit of the integrated circuit design is formed by a Bipolar process.
153. The library of claim 149, wherein the integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
154. The library of claim 149, wherein the integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
155. The library of claim 149, wherein the one or more cells includes at least one standard cell
156. The library of claim 149, wherein the one or more cells includes at least one gate array cell.
157. The library of claim 149, wherein the one or more cells includes at least one analog cell.
158. The library of claim 149, wherein the one or more cells includes at least one analog mixed signal cell.
159. The library of claim 149, wherein the one or more cells includes at least one analog and digital cell.
160. The library of claim 149, wherein the one or more cells includes at least one functional block cell.
161. The library of claim 149, wherein the angle is about 45 degrees.
162. A cell library, comprising:
a first plurality of one or more cells for an integrated circuit design, the first plurality of one or more cells having a first plurality of one or more structures on one or more edges of the first plurality of one or more cells, wherein the first plurality of one or more cells is adapted to be positioned by a second plurality of one or more cells, the second plurality of one or more cells having a second plurality of one or more structures on one or more edges of the second plurality of one or more cells, such that at least one structure of the first plurality of one or more structures overlaps at least one structure of the second plurality of one or more structures.
163. The library of claim 162, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
164. The library of claim i62, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
165. The library of claim 162, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
166. The library of claim 162, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
167. The library of claim 162, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
168. The library of claim 162, wherein the one or more cells includes at least one standard cell
169. The library of claim 162, wherein the one or more cells includes at least one gate array cell.
170. The library of claim 162, wherein the one or more cells includes at least one analog cell.
171. The library of claim 162, wherein the one or more cells includes at least one analog mixed signal cell.
172. The library of claim 162, wherein the one or more cells includes at least one analog and digital cell.
173. The library of claim 162, wherein the one or more cells includes at least one functional block cell.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A hoist apparatus comprising:
a frame;
a drum mounted on the frame for rotation about a drum axis;
a motor connected to the drum for selectively rotating the drum in opposite wind-up and wind-off directions about the drum axis;
a rope wound around the drum such that the rope winds on to and off of the drum in response to rotation of the drum in the wind-up and wind-off directions, respectively;
a switch mounted to the frame and preventing the motor from rotating the drum when the switch is actuated to a stop motor position; and
a rope sensing device pivotable between a sensing position and a fouled position, the rope sensing device including a lever arm having a first end portion, a second end portion, and a pivot point located between the first and second end portions along the lever arm, the lever arm being pivotably connected to the frame at the pivot point, a follower connected to the first end portion and positioned adjacent and spaced from the drum such that the rope winds on to the drum spaced from and relative to the follower when the rope sensing device is in the sensing position, and a switch actuator connected to the second end portion adjacent the switch, the rope sensing device being biased towards and positioned in the sensing position until a rope fouling event occurs and causes the rope to contact the follower and pivot the lever arm from the sensing position to the fouled position, the switch actuator actuating the switch to the motor stop position when the rope sensing device is in the fouled position.
2. A hoist apparatus according to claim 1 and further comprising a control operably connected to the motor and the switch, wherein the control controls rotation of the drum, and wherein the switch signals the control to prevent the motor from rotating the drum when the switch is actuated to the stop motor position.
3. A hoist apparatus according to claim 1 wherein the drum includes a helical groove in which the rope is reeved as the rope winds on to the drum, and wherein a rope fouling event occurs when the rope leaves the helical groove.
4. A hoist apparatus according to claim 1 and further comprising a load engaging mechanism connected to the rope such that the load engaging mechanism moves upward when the rope winds on to the drum and moves downward when the rope winds off of the drum.
5. A hoist apparatus according to claim 1 wherein the follower includes a roller connected to the lever arm for rotation about a roller axis, and wherein the roller axis is substantially parallel to the drum axis.
6. A hoist apparatus according to claim 5 wherein the roller includes a polyurethane cover.
7. A hoist apparatus according to claim 5 wherein the rope sensing device further includes a bearing that connects the roller to the lever arm for rotation about the roller axis.
8. A hoist apparatus according to claim 1 wherein the rope sensing device further includes a bearing that pivotably connects the lever arm to the frame at the pivot point.
9. A hoist apparatus according to claim 1 wherein the lever arm is biased towards the sensing position by a spring.
10. A hoist apparatus according to claim 9 further comprising a first spring mount connected to the frame, wherein the rope sensing device includes a second spring mount connected to the lever arm, wherein the spring is connected between the first and second spring mounts, and wherein at least one of the first and second spring mounts is adjustable to adjust the bias force exerted by the spring on the lever arm.
11. A hoist apparatus according to claim 1 wherein the switch actuator includes an actuating portion, and wherein the position of the actuating portion relative to the switch is adjustable.
12. A hoist apparatus according to claim 1 wherein the switch actuator linearly actuates the switch.
13. A hoist apparatus according to claim 1 wherein the position of the follower portion relative to drum is adjustable.
14. A hoist apparatus according to claim 13 wherein a portion of the frame contacts a portion of the lever arm to establish the position of the follower portion relative to the drum.
15. A hoist apparatus according to claim 1 wherein the rope is wound around the drum in a double-reeve rope arrangement, and further comprising a second rope sensing device positioned adjacent the drum to detect a rope fouling event.
16. A hoist apparatus according to claim 15 wherein the follower of the first mentioned rope sensing device extends approximately one half of the axial length of the drum to sense a first portion of the double-reeve rope arrangement winding on to the drum, and wherein a follower of the second rope sensing device extends approximately the other one half of the axial length of the drum to sense a second portion of the double-reeve rope arrangement winding on to the drum.
17. A hoist apparatus according to claim 1 wherein the switch actuator is spaced from the pivot point by a distance that allows for complete actuation of the switch to the motor stop position when a rope fouling event occurs.
18. A hoist apparatus according to claim 1 wherein the lever arm includes an L-shaped member, and wherein the L-shaped member includes a first leg portion and a second leg portion joined to the first leg portion roughly at the pivot point.
19. A hoist apparatus according to claim 18 wherein the first leg portion defines a first length, wherein the second leg portion defines a second length, and wherein the first and second lengths are approximately equal.
20. A hoist apparatus according to claim 18 wherein the follower is connected to the first leg portion, and wherein the switch actuator is connected to the second leg portion.
21. A hoist apparatus according to claim 18 wherein the first and second leg portions are spaced by approximately ninety degrees.
22. A hoist apparatus comprising:
a frame;
a drum mounted on the frame for rotation about a drum axis;
a motor connected to the drum for selectively rotating the drum in opposite wind-up and wind-off directions about the drum axis;
a rope wound around the drum such that the rope winds on to and off of the drum in response to rotation of the drum in the wind-up and wind-off directions, respectively, the rope having a predetermined radial position beyond which it is not desirable to wind rope on to the drum;
a switch mounted to the frame and preventing the motor from rotating the drum when the switch is actuated to a stop motor position; and
a rope sensing device pivotable between a sensing position and a fouled position, the rope sensing device including a lever arm having a first end portion, a second end portion, and a pivot point located between the first and second end portions along the lever arm, the lever arm being pivotably connected to the frame at the pivot point, a roller connected to the first end portion for rotation about a roller axis, the roller axis being substantially parallel to the drum axis, the roller being positioned adjacent and spaced from the drum such that the rope winds on to the drum spaced from and relative to the follower when the rope sensing device is in the sensing position, and a switch actuator connected to the second end portion adjacent the switch, the rope sensing device being biased towards and positioned in the sensing position until a rope fouling event occurs and causes the rope to contact the follower and pivot the lever arm from the sensing position to the fouled position, the switch actuator actuating the switch to the motor stop position when the rope sensing device is in the fouled position, a rope fouling event occurring when the rope is positioned radially outward of the predetermined radial position beyond which it is not desirable to wind rope on to the drum.
23. A hoist apparatus comprising:
a frame;
a drum mounted on the frame for rotation about a drum axis;
a motor connected to the drum for selectively rotating the drum in opposite wind-up and wind-off directions about the drum axis;
a rope wound around the drum such that the rope winds on to and off of the drum in response to rotation of the drum in the wind-up and wind-off directions, respectively;
a switch mounted to the frame and preventing the motor from rotating the drum when the switch is actuated to a stop motor position; and
a rope sensing device pivotable between a sensing position and a fouled position, the rope sensing device including a lever arm having a first end portion, a second end portion, and a pivot point located between the first and second end portions along the lever arm, the lever arm being pivotably connected to the frame at the pivot point, a roller connected to the first end portion and positioned adjacent and spaced from the drum by a first distance such that the rope winds on to the drum spaced from and relative to the follower when the rope sensing device is in the sensing position, the first distance being adjustable, and a switch actuator connected to the second end portion and positioned adjacent the switch, the position of the switch actuator relative to the switch being adjustable, the rope sensing device being biased by a spring towards and positioned in the sensing position until a rope fouling event occurs and causes the rope to contact the follower and pivot the lever arm from the sensing position to the fouled position, the spring exerting a biasing force, the biasing force being adjustable, the switch actuator actuating the switch to the motor stop position when the rope sensing device is in the fouled position.