1. A control circuit, comprising:
a variable transmittance optical filter comprising a first and a second electrode and a switching material in contact with the first and second electrodes, wherein the switching material is capable of transitioning from a light state to a dark state on exposure to ultraviolet radiation and from the dark state to the light state with application of an electric voltage across the first and second electrodes;
power control electronics comprising a switch for electrically coupling to a power source, the power control electronics electrically coupled to the first and second electrodes and operable to:
dissipate any charge on the optical filter by shorting the first and second electrodes together, thereby facilitating transition of the switching material from the light state to the dark state upon exposure of the switching material to ultraviolet radiation; and
transition the optical filter from the dark state to the light state by applying a voltage from the power source across the first and second electrodes; and
a DC-DC regulator or a DC-DC converter electrically coupled in series with the power control electronics, wherein the power control electronics receives a DC voltage from the DC-DC regulator or DC-DC converter when the power source is electrically coupled to the power control electronics and the DC-DC regulator or the DC-DC converter matches the DC voltage to a voltage required by the optical filter in order to trigger lightening.
2. The control circuit of claim 1, further comprising an AC adapter, wherein the DC-DC regulator or the DC-DC converter is electrically coupled in series between the AC adapter and the power control electronics when the power source is electrically coupled to the power control electronics.
3. The control circuit of claim 1, wherein the power control electronics further comprise a timing circuit and a first user-controlled sensor, and wherein the power control electronics use the timing circuit to apply the voltage across the first and second electrodes for a fixed period of time in response to receiving a signal from the first user-controlled sensor, the fixed period of time preset to be the amount of time required for the optical filter to transition from the dark state to the light state.
4. The control circuit of claim 1, wherein the switching material comprises part of a window of a building or vehicle or part of a lens.
5. The control circuit of claim 3, wherein the power control electronics further comprise a second user-controlled sensor and wherein the power control electronics use the timing circuit to apply, in response to receiving a signal from the second user-controlled sensor, the voltage across the first and second electrodes for a period of time longer than the fixed period of time.
6. The control circuit of claim 3, wherein the power control electronics further comprise a second user-controlled sensor and the power control electronics cease applying the voltage to the switching material in response to receiving a signal from the second user-controlled sensor while the power control electronics are applying the voltage to the first and second electrodes.
7. The control circuit of claim 6, wherein the power control electronics short the first and second electrodes together in response to receiving the signal from the second user-controlled sensor.
8. The control circuit of claim 1, wherein the power control electronics further comprise a user-controlled sensor and the power control electronics short the first and second electrodes together in response to receiving a signal from the user-controlled sensor.
9. The control circuit of claim 1, wherein the power control electronics further comprise a light sensor and the power control electronics short the first and second electrodes together upon receiving a signal from the light sensor indicating a certain level of ambient brightness around the optical filter.
10. The control circuit of claim 1, wherein the power control electronics further comprise a user-controlled sensor and a light sensor, and wherein the power control electronics maintain the voltage across the first and second electrodes in response to a first signal from the user-controlled sensor in order to maintain the optical filter in the light state when the light sensor indicates a certain level of ambient brightness around the optical filter.
11. The control circuit of claim 10, wherein the power control electronics shorts the first and the second electrodes together in response to a second signal from the user-controlled sensor that is received after the first signal.
12. The control circuit of claim 1, wherein the switch comprises a multi-state control device operable to permit a user to select an intermediate transmittance for the optical filter, wherein the power control electronics applies the voltage across the first and second electrodes for a duration sufficient to achieve the intermediate state.
13. The control circuit of claim 1, wherein the switch comprises a multi-state control device operable to permit a user to select an intermediate transmittance for the optical filter, wherein the power control electronics applies the voltage across the first and second electrodes to achieve the intermediate state based on feedback from one or more light sensors.
14. The control circuit of claim 1, wherein the power control electronics further comprise a voltage or a current sensor that senses when the switching material has transitioned to the light state, and wherein the power control electronics cease to apply the voltage across the first and second electrodes when the switching material has transitioned to the light state.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of making a buried plate region in a semiconductor substrate, comprising:
forming a trench in a semiconductor substrate, the trench having a trench sidewall, the sidewall including an upper portion, and a lower portion disposed below the upper portion;
forming a dopant source layer along the lower portion of the trench sidewall, the dopant source layer not being disposed along the upper portion of the trench sidewall;
forming a barrier layer along the upper portion of the trench sidewall; and
annealing the semiconductor substrate to drive a dopant from the dopant source layer into the semiconductor substrate adjacent to the lower portion of the trench sidewall.
2. A method as claimed in claim 1, wherein a cap layer is formed overlying the dopant source layer prior to said annealing.
3. A method as claimed in claim 1, wherein the barrier layer is formed by thermal nitridation.
4. A method as claimed in claim 3, wherein the barrier layer has a thickness of between about 10 angstroms and angstroms.
5. A method as claimed in claim 1, wherein the barrier layer includes at least one material selected from the group consisting of cobalt silicide, nickel silicide, tungsten silicide, titanium silicide, titanium nitride, tantalum nitride and silicon carbide.
6. A method as claimed in claim 2, wherein the cap layer consists essentially of an undoped oxide.
7. A method as claimed in claim 1, further comprising removing the cap layer and the dopant source layer from the trench sidewall after the annealing, and thereafter removing oxidized material of the substrate to widen the trench in the region of the lower portion.
8. A method as claimed in claim 1, wherein the dopant source layer is formed by depositing arsenic doped glass (ASG) at a temperature of about 700\xb0 C.
9. A method of making a trench capacitor having a buried plate formed according to a method as claimed in claim 1, further comprising:
forming a node dielectric along the lower portion of the trench sidewall after removing the dopant source layer; and
depositing at least one of a conductive and a semiconducting material onto the node dielectric as a second plate opposing the buried plate.
10. A method of making a buried plate region in a substrate including a single-crystal semiconductor, comprising:
vertically etching the substrate to pattern a vertically elongated trench in the substrate;
forming a dopant source layer on a lower portion of a sidewall of the trench;
selectively epitaxially growing a layer consisting essentially of semiconductor material onto a portion of the single-crystal semiconductor exposed at an upper portion of the trench sidewall, the upper portion being disposed vertically above the lower portion of the trench sidewall; and
annealing to drive a dopant from the dopant source layer into the single-crystal semiconductor of the substrate adjacent to the lower portion to form a buried plate.
11. A method as claimed in claim 10, wherein at least a portion of the thickness of the epitaxially grown layer is oxidized during the annealing.
12. A method as claimed in claim 11, wherein the dopant source layer includes a doped oxide material, the method further comprising etching the oxidized portion and the doped oxide material after the annealing, the etching being performed selective to the single-crystal semiconductor included in the substrate.
13. A method as claimed in claim 12, wherein the single-crystal semiconductor of the substrate is initially doped p-type and the dopant source layer includes an n-type dopant such that the buried plate includes the n-type dopant, the method further comprising etching the single-crystal semiconductor disposed in the buried plate selective to the p-type doped single-crystal semiconductor, such that a dimension of the trench is widened in the region of the lower portion of the trench sidewall.
14. A method as claimed in claim 13, wherein the single-crystal semiconductor of the substrate consists essentially of silicon, the epitaxially grown layer including an etch distinguishable semiconductor alloy, and only a portion of the thickness of the epitaxially grown layer is oxidized during the annealing, such that a portion of the epitaxially grown layer remains as a mask disposed on the upper portion of the trench sidewall, the method further comprising etching the single-crystal semiconductor disposed in the buried plate selective to the material of the epitaxially grown layer to widen a dimension of the trench in the region of the lower portion of the trench sidewall.
15. A method as claimed in claim 14, wherein the epitaxially grown layer consists essentially of at least one semiconductor alloy selected from the group consisting of SiGe and SiC.
16. A method of forming a trench capacitor in a semiconductor substrate, comprising:
patterning a trench through an opening in a pad stack by vertically etching the substrate selective to a material of the pad stack, the trench having a trench sidewall including a lower portion and an upper portion disposed above the lower portion;
forming a dopant source layer over a lower portion of the trench sidewall, such that the dopant source layer is not disposed over an upper portion of the trench sidewall;
forming a layer covering the upper portion of the trench sidewall;
annealing to drive a dopant from the dopant source layer into the single-crystal semiconductor material of the substrate adjacent to the lower portion to form a buried plate;
removing the dopant source layer;
forming a node dielectric along the lower portion of the trench sidewall; and
forming a node electrode on a side of the node dielectric opposite the buried plate to form the trench capacitor.
17. A method as claimed in claim 16, wherein the covering layer is formed by thermal nitridation, the dopant source layer includes arsenic doped glass (ASG), and the method further comprises widening the lower portion prior to forming the node dielectric and prior to forming the node electrode.
18. A method as claimed in claim 17, wherein the covering layer functions as a barrier to prevent diffusion of a dopant from the dopant source layer into the semiconductor substrate adjacent to the upper portion.
19. A method as claimed in claim 16, wherein the covering layer functions as a sacrificial layer, a portion of the thickness of which is at least partially oxidized during the annealing, the oxidized portion of the covering layer being thereafter removed during the removal of the dopant source layer.
20. A method as claimed in claim 19, further comprising widening the lower portion prior to forming the node dielectric and prior to forming the node electrode.