What is claimed is:
1. A composite material comprising; a quartz glass phase; and a complex compound phase compounded with the quartz glass phase, which is made of one or more compounds selected from a group of silicon carbide, silicon nitride, silicon, titanium nitride and titanium carbide, as a main ingredient.
2. The composite material according to claim 1, wherein an amount of the quartz glass phase is 10-95 wt %.
3. The composite material according to claim 2, wherein an amount of the quartz glass phase is 80-95 wt %.
4. The composite material according to claim 1, wherein the compound is selected from a group of silicon carbide, silicon nitride and silicon.
5. The composite material according to claim 1, wherein the compound is selected from a group of silicon carbide, silicon, titanium nitride and titanium carbide.
6. The composite material according to claim 1, wherein an open porosity is lower than 15%.
7. The composite material according to claim 6, wherein a total amount of impurities other than quartz glass, elements constituting the compound and halogen is lower than 0.1 wt %, and an open porosity is lower than 5%.
8. A method of producing a composite material, comprising the steps of:
mixing a quartz glass powder and a compound powder made of one or more compounds selected from the group of silicon carbide, silicon nitride, silicon, titanium nitride and titanium carbide to obtain mixtures;
forming the mixtures to obtain a formed body; and
sintering the formed body at a temperature which is lower than the melting point of quartz glass and is lower than the melting point of the compound.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A high electrical performance semiconductor package, comprising:
a carrier having a first surface, a second surface opposite to the first surface, and a plurality of conductive vias for electrically connecting the first surface to the second surface;
at least one chip attached to the first surface of the carrier;
a plurality of via lands disposed on a peripheral area of the first surface of the carrier and electrically connected to the conductive vias;
a plurality of fingers disposed around the chip and electrically connected to the corresponding via lands by conductive traces formed on the first surface of the carrier;
a plurality of bonding wires for electrically connecting the chip to the fingers, wherein lengths of the bonding wires for transmitting differential pair signals are substantially equal, and lengths of the conductive traces for transmitting the differential pair signals are substantially equal; and
a plurality of conductive regions disposed on the second surface of the carrier and electrically connected to the conductive vias.
2. The high electrical performance semiconductor package of claim 1, wherein the carrier is a substrate.
3. The high electrical performance semiconductor package of claim 1, wherein the plurality of via lands are arranged in multiple rows on the peripheral area of the first surface of the carrier.
4. The high electrical performance semiconductor package of claim 1, wherein the plurality of via lands are located at edges of the conductive vias on the first surface of the carrier.
5. The high electrical performance semiconductor package of claim 1, wherein the plurality of conductive regions are arranged in multiple rows on a peripheral area of the second surface of the carrier.
6. The high electrical performance semiconductor package of claim 1, wherein the plurality of conductive regions are located close to the conductive vias on the second surface of the carrier.
7. The high electrical performance semiconductor package of claim 1, wherein a portion of the fingers are spaced apart from the chip by a substantially constant distance to make the lengths of the bonding wires for transmitting the differential pair signals substantially equal.
8. The high electrical performance semiconductor package of claim 1, wherein a portion of the conductive traces are curved to make the lengths of the conductive traces for transmitting the differential pair signals substantially equal.
9. The high electrical performance semiconductor package of claim 1, wherein all the fingers are spaced apart from the chip by a substantially constant distance.
10. The high electrical performance semiconductor package of claim 1, wherein all the bonding wires are substantially equal in length.
11. The high electrical performance semiconductor package of claim 1, wherein all the conductive traces for electrically connecting the fingers to the via lands are substantially equal in length.
12. The high electrical performance semiconductor package of claim 1, wherein the conductive regions are lands.
13. The high electrical performance semiconductor package of claim 1, wherein the conductive regions are ball pads.
14. The high electrical performance semiconductor package of claim 1, further comprising an encapsulant for encapsulating the chip and the bonding wires.