1. A method for clearing the memory of a Field Programmable Gate Array (\u201cFPGA\u201d) Integrated Chip (\u201cIC\u201d), comprised of a plurality of cores, said method comprising:
clearing memory of said plurality of cores;
sequentially verifying completion of said clearing memory act for each core of said plurality of cores;
providing a programming ready signal to all cores of said plurality of cores when a last core of said plurality of cores has completed said clearing memory act;
providing an enable memory clear query signal to a first core of said plurality of cores;
clearing memory of said plurality of cores;
determining whether said first core has completed its said clearing memory act;
providing a first core memory cleared signal, if said first core has completed its said clearing memory act;
providing a first core memory cleared out signal;
repeating in a sequential manner the acts of determining whether a next core of said plurality of cores has completed its said clearing memory act, providing a said next core memory cleared signal, if said next core has completed its clearing memory act, and providing a said next core memory cleared out signal, until said last core has completed its clearing memory act;
providing a said last core’s memory cleared signal; and
providing a said programming read signal to said all cores.
2. A method for sequentially programming with bitstream data each core of a plurality of cores in an FPGA IC, said method comprising:
sending said bitstream data to a first core of said plurality of cores;
sending the balance of said bitstream data to a next core of said plurality of cores after said first core has received its portion of bitstream data;
repeating in a sequential manner the acts of sending a balance of said bitstream data to a following core of said plurality of cores after an immediately preceding core of said plurality of cores has received its portion of bitstream data, until a last core of said plurality of cores has received its portion of bitstream data; and
sending a program start signal to all cores of said plurality of cores.
3. The method of claim 2 further comprising:
providing to said first core an enable programming complete query signal;
sending said bitstream data to said first core;
providing a first core programmed signal, when said first core has received all its said bitstream data;
providing a program ok out signal;
sending the balance of said bitstream data from said first core to a next core of said plurality of cores;
repeating the acts of providing a next core programmed signal, when said next core has received all its said bitstream data, providing a next core program ok out signal, sending the balance of said bitstream data from a said next core to a subsequent core of said plurality of cores, in a sequential manner until a last core of said plurality of cores has received its bitstream data;
providing a said last core programmed signal; and
providing a run program signal to said all cores.
4. An FPGA IC comprising:
a plurality of cores, wherein each core comprises:
an enable memory clear query signal coupled to an input of a first logic module;
a power up module coupled to an input of said first logic module;
a memory cleared out signal coupled to an output of said first logical module;
a programming module coupled to a programming ready signal;
wherein the memory cleared out signal of each non-last core is coupled to the enable memory clear query signal of a subsequent core; and
wherein the memory cleared out signal of a last core is coupled to said programming ready signal of each core.
5. The plurality of cores of claim 4, wherein each core further comprises:
a program okay out signal coupled to a second logic module;
a core programmed signal coupled to said programming module and to an input of said second logic module;
a program okay out signal coupled to the output of said second logic module;
a data out signal coupled to said programming module
a data in signal coupled to each non-first core said programming module;
a start up module coupled to a run program signal; and
wherein each non-last core said program okay out signal is coupled to a subsequent core’s enable programming complete query signal, wherein each non-first core data in signal is coupled to said data out signal of a preceding core; wherein a first core’s programming module is coupled to a data bus interface, and wherein said program okay out signal of a last core is coupled to said run program signal of each core.
6. The IC of claim 5, wherein a data fetch clock signal couples each adjacent core’s programming module.
7. The IC of claim 5 wherein the first and second logic units are AND gates.
8. The IC of claim 5, wherein the data bus interface is a serial interface.
9. The IC of claim 5, wherein the data bus interface is a parallel interface.
10. An FPGA IC comprised of a plurality of cores, said IC comprising:
means for providing an enable memory clear query signal to a first core of said plurality of cores;
means for clearing memory of said plurality of cores;
means for determining whether said first core has completed its said clearing memory act;
means for providing a first core memory cleared signal, if said first core has completed its said clearing memory act;
means for providing a first core memory cleared out signal;
means for repeating in a sequential manner the acts of determining whether a next core of said plurality of cores has completed its said clearing memory act, providing a said next core memory cleared signal, if said next core has completed its clearing memory act, and providing a said next core memory cleared out signal, until said last core has completed its clearing memory act;
means for providing a said last core’s memory cleared signal; and
means for providing a said programming read signal to said all cores.
11. An FPGA IC with a plurality of cores, said IC comprising:
means for providing to said first core an enable programming complete query signal;
means for sending said bitstream data to said first core;
means for providing a first core programmed signal, when said first core has received all its said bitstream data;
means for providing a program ok out signal;
means for sending the balance of said bitstream data from said first core to a next core of said plurality of cores;
means for repeating the acts of providing a next core programmed signal, when said next core has received all its said bitstream data, providing a next core program ok out signal, sending the balance of said bitstream data from a said next core to a subsequent core of said plurality of cores, in a sequential manner until a last core of said plurality of cores has received its bitstream data;
means for providing a said last core programmed signal; and
means for providing a run program signal to said all cores.
12. A method for clearing the memory of an FPGA IC, comprised of one core, said method comprising:
clearing memory of said core;
verifying completion of said clearing memory act of said core;
providing a programming ready signal to said core when said core has completed said clearing memory act;
providing an enable memory clear query signal to said core;
clearing memory of said core;
determining whether said core has completed its said clearing memory act;
providing a core memory cleared signal, if said core has completed its said clearing memory act;
providing a core memory cleared out signal; and
providing a said programming read signal to said core.
13. A method for programming with bitstream data a core in a FPGA IC, said method comprising:
sending said bitstream data to said core;
sending a program start signal to said core;
providing to said core an enable programming complete query signal;
sending said bitstream data to said core;
providing a core programmed signal, when said core has received all its said bitstream data;
providing a program ok out signal;
providing a core programmed signal; and
providing a run program signal to said core.
14. An FPGA IC comprising:
a core, wherein said core comprises:
an enable memory clear query signal coupled to an input of a first logic module;
a power up module coupled to an input of said first logic module;
a memory cleared out signal coupled to an output of said first logical module;
a programming module coupled to a programming ready signal; and
wherein the memory cleared out signal of said core is coupled to said programming ready signal of said core.
15. The core of claim 14, wherein said core further comprises:
a program okay out signal coupled to a second logic module;
a core programmed signal coupled to said programming module and to an input of said second logic module;
a program okay out signal coupled to the output of said second logic module;
a start up module coupled to a run program signal; and
wherein said core’s programming module is coupled to a data bus interface, and wherein said program okay out signal of said core is coupled to said run program signal of said core.
16. The IC of claim 15 wherein the first and second logic units are AND gates.
17. The IC of claim 15, wherein the data bus interface is a serial interface.
18. The IC of claim 15, wherein the data bus interface is a parallel interface.
19. An FPGA IC comprised of a core, said IC comprising:
means for providing an enable memory clear query signal to said core;
means for clearing memory of said core;
means for determining whether said core has completed its said clearing memory act;
means for providing a core memory cleared signal, if said core has completed its said clearing memory act;
means for providing a said core memory cleared out signal;
means for providing a said core memory cleared signal; and
means for providing a said core programming read signal.
20. An FPGA IC with a core, said IC comprising:
means for providing to said core an enable programming complete query signal;
means for sending said bitstream data to said core;
means for providing said core programmed signal, when said core has received all its said bitstream data;
means for providing a program ok out signal; and
means for providing a run program signal to said core.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for recovering nylon from a nylon-containing material, comprising:
contacting the nylon-containing material with an alkanol-containing solvent in a mixing vessel, wherein at least a portion of the mixture of nylon-containing material and alkanol-containing solvent is withdrawn from the mixing vessel and returned to the mixing vessel at a high flow rate;
increasing the temperature and pressure of the mixture until a pressure is reached that is higher than the equilibrium pressure of the alkanol-containing solvent, and until the temperature is between 130\xb0 C. and 155\xb0 C. thereby dissolving the nylon in the alkanol-containing solvent;
removing the alkanol-containing solvent containing dissolved nylon from any undissolved solids; and
decreasing the temperature, or pressure, or both, of the alkanol-containing solvent containing dissolved nylon to precipitate the dissolved nylon.
2. The method of claim 1, wherein the temperature of mixture is increased in a plug flow heat exchanger.
3. The method of claim 2, wherein the plug flow heat exchanger comprises a coiled tube heat exchanger.
4. The method of claim 2 wherein the plug flow heat exchanger comprises a stacked single pass jacketed heat exchanger.
5. The method of claim 1, further comprising concentrating, dewatering, or otherwise increasing the percent solids concentration of the precipitated nylon.
6. The method of claim 5, wherein the concentrating, dewatering or otherwise increasing the concentration of the precipitated nylon comprises subjecting the precipitated nylon containing stream to vibratory shear enhanced processing membrane filtration.
7. The method of claim 5, wherein the concentrating, dewatering or otherwise increasing the concentration of the precipitated nylon comprises subjecting the precipitated nylon containing stream to a filter press.
8. The method of claim 5, wherein the concentrating, dewatering or otherwise increasing the concentration of the precipitated nylon comprises subjecting the precipitated nylon containing stream to vibratory shear enhanced processing membrane filtration, and a filter press.
9. The method of claim 5, wherein concentrating, dewatering or otherwise increasing the concentration of the precipitated nylon increases the solids content of the precipitated nylon in the liquid to at least 5%.
10. The method of claim 9, wherein the solids content is increased to 5-10%.
11. The method of claim 9, wherein the solids content is increased to at least 25%.
12. The method of claim 9, further comprising drying the dewatered, concentrated precipitated nylon in a drier operating under a vacuum or in an inert gas environment.
13. The method of claim 12, wherein the drying occurs in a spin flash drier.
14. The method of claim 12, wherein the drying occurs in a paddle drier comprising agitating plows and choppers.
15. The method of claim 1, wherein the mixing comprises withdrawing a portion of the mixer contents through a conduit by a splitter pump, diverting a portion of the withdrawn material to further processing, and returning the remainder of the withdrawn portion to the mixer.
16. The method of claim 1, wherein the alkanol-containing solvent comprises an alkanol selected from the group consisting of methanol, ethanol, propanols, butanols, and mixtures thereof.
17. The method of claim 1, wherein the alkanol-containing solvent comprises a mixture of alkanol and water.
18. The method of claim 17, wherein the alkanol is present in an amount ranging from about 40 wt % to about 90 wt % of the solvent.
19. The method of claim 18, wherein the alkanol-containing solvent comprises a mixture of about 80 wt % ethanol in water.
20. The method of claim 1, wherein the pressure during the contacting ranges from about 300 psig to about 500 psig.
21. The method of claim 1, wherein the elevated temperature is about 140\xb0 C.
22. The method of claim 1, wherein the pressure higher than the equilibrium pressure of the alkanol-containing solvent at the elevated temperature is attained by introducing an inert gas into the system.
23. The method of claim 1, wherein the pressure higher than the equilibrium pressure of the alkanol-containing solvent at the elevated temperature results at least in part from the pressure head of the alkanol-containing solvent in the system.
24. The method of claim 1, wherein the nylon-containing waste material comprises nylon-containing floor covering materials.
25. The method of claim 24, wherein the nylon-containing floor covering materials comprise carpet or carpet tile, or mixtures thereof.
26. The method of claim 25, wherein the carpet or carpet tile contains nylon 6,6.
27. A method for recovering nylon from a nylon-containing material, comprising:
contacting the nylon-containing material with an alkanol-containing solvent in a mixing vessel, wherein at least a portion of the mixture of nylon-containing material and alkanol-containing solvent is withdrawn from the mixing vessel by a splitter pump and returned to the mixing vessel at a high flow rate;
increasing the temperature and pressure of the mixture until a pressure is reached that is higher than the equilibrium pressure of the alkanol-containing solvent, and until the temperature is between 130\xb0 C. and 155\xb0 C. thereby dissolving the nylon in the alkanol-containing solvent;
removing the alkanol-containing solvent containing dissolved nylon from any undissolved solids;
decreasing the temperature, or pressure, or both, of the alkanol-containing solvent containing dissolved nylon to precipitate the dissolved nylon;
concentrating, dewatering, or otherwise increasing the concentration of the precipitated nylon;
drying the dewatered, concentrated precipitated nylon in a drier.
28. A method for increasing the tenacity of nylon fiber, comprising:
dissolving a feedstock nylon fiber in a solvent comprising an alkanol at an elevated temperature between 130\xb0 C. and 155\xb0 C. and at a dissolution pressure above the equilibrium vapor pressure of the solvent at the dissolution temperature;
filtering undissolved solids from the solution;
precipitating nylon from solution by decreasing pressure, temperature, or both of the solution, to form a precipitated mixture;
concentrating the precipitated nylon by removing solvent from the precipitated mixture to form a concentrated mixture;
drying the concentrated mixture to form solid nylon;
extruding the solid nylon into fiber having tenacity increased over that of the feedstock nylon fiber.
29. A method for increasing the molecular weight of feedstock nylon, comprising:
dissolving a feedstock nylon in a solvent comprising an alkanol at an elevated temperature between 130\xb0 C. and 155\xb0 C. at a dissolution pressure above the equilibrium vapor pressure of the solvent at the dissolution temperature;
filtering undissolved solids from the solution;
precipitating nylon from solution by decreasing pressure, temperature, or both of the solution, to form a precipitated mixture;
concentrating the precipitated nylon by removing solvent from the precipitated mixture to form a concentrated mixture;
drying the concentrated mixture to form solid nylon having a molecular weight substantially increased over that of the feedstock nylon.
30. The method of claim 29, wherein the molecular weight of the solid nylon is at least 8 kdalton higher than that of the feedstock nylon.
31. The method of claim 30, wherein the molecular weight of the solid nylon is at least 10 kdalton higher than that of the feedstock nylon.