1. An improved detector of transformer interturn short circuit using voltage differential, comprising a single-phase transformer in a single-phase high voltage power supply circuit, the single-phase transformer comprising a high voltage winding and a low voltage winding, a potential transformer being provided on a high voltage side of the single-phase transformer, a high voltage being drawn from a tap of the high voltage winding connected to a first converter and converted to a first voltage by the first converter, a second voltage being drawn from the potential transformer connected to a second converter and converted to a second voltage by the second converter;
wherein a first comparison is conducted between the first voltage and the second voltage and a first result is outputted, then a low voltage is drawn from a tap of the low voltage winding connected to a third converter and converted to a third voltage by the third converter, a second comparison is conducted between the third voltage and the fourth voltage converted by the fourth converter from full voltage of the low voltage winding and a second result is outputted; and
wherein the first result and the second result are compared with predetermined values to determine whether short circuit occurs.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of making an array of non-volatile memory cells on a semiconductor substrate, comprising:
forming a first set of trenches in a surface of the substrate that are spaced apart in a first direction and elongated in a second direction across the substrate surface, the first and second directions being orthogonal with each other,
forming source and drain regions in at least bottom surfaces of the first set of trenches along their lengths,
isotropically depositing first material over and into the first set of trenches,
anisotropically removing the deposited first material in a manner to leave spacers along opposite side walls of the first set of trenches with spaces therebetween in the first direction, wherein the spacers become charge storage elements of the array of memory cells, and
forming conductive first control gates that extend in the second direction in the spaces in the first set of trenches between the spacers and conductive first control gate lines that extend in the second direction over the first control gates to which they are electrically connected.
2. The method of claim 1, additionally comprising forming conductive shields within the substrate between the first set of trenches in the second direction, and wherein forming the conductive control gate lines includes forming said lines over and in electrical contact with the shields.
3. The method of claim 2, wherein forming the conductive shields includes forming a second set of trenches in the surface of the substrate between the first trenches in the second direction, and thereafter forming the conductive shields in the second set of trenches.
4. The method of claim 1, additionally comprising:
prior to depositing the first material, forming a second material between the trenches in at least the first direction,
thereafter depositing the first material over the second material and over and into the first set of trenches,
anisotropically removing the deposited first material in a manner to leave spacers along opposed side walls of the trenches and walls of the second material above the trenches, and
thereafter removing the deposited second material, thereby to leave the spacers extending a distance above the surface of the substrate.
5. The method of claim 4, additionally comprising:
forming conductive second control gates in spaces between the trenches in the first direction along with second control gate lines that extend in the first direction over second control gates to which they are electrically connected, the second control gates being formed to be field coupled with both the substrate surface between the trenches in the first direction and the charge storage elements extending a distance above the surface of the substrate.
6. The method of claim 5, wherein the second control gates and second control gate lines are formed as a unitary structure by a common process.
7. The method of claim 1, wherein depositing first material includes depositing polysilicon, wherein the resulting charge storage element spacers of polysilicon become conductive floating gates.
8. The method of claim 1, wherein the forming of said conductive first control gates and conductive first control gate lines includes electrically connecting said conductive first control gates and conductive first control gate lines.
9. The method of claim 1, further comprising forming select gates in the first direction and outside the trenches and connecting the select gates to word lines elongated in the first direction and spaced apart in the second direction.
10. A method of making an array of non-volatile memory cells on a semiconductor substrate, comprising:
forming trenches into a surface of the substrate that are spaced apart in a first direction and elongated in a second direction across the substrate surface, the first and second directions being orthogonal with each other,
forming source and drain regions in at least bottom surfaces of the trenches along their lengths,
depositing first polysilicon material across the substrate and into the first set of trenches,
anisotropically removing the deposited first polysilicon material in a manner to leave conductive spacers along opposite side walls of the trenches with spaces therebetween in the first direction,
forming control gates in the spaces between the spacers,
separating the spacers into floating gates, and
forming select gates over the substrate surface in between the trenches in the first direction and connecting them to word lines elongated in the first direction and spaced apart in the second direction.
11. A method of making an array of non-volatile memory cells on a semiconductor substrate, comprising:
forming a first set of trenches into a surface of the substrate that are spaced apart in a first direction and elongated in a second direction across the substrate surface, the first and second directions being orthogonal with each other,
forming source and drain regions in at least bottom surfaces of the first set of trenches along their lengths,
depositing first polysilicon material across the substrate and into the first set of trenches,
anisotropically removing the deposited first polysilicon material in a manner to leave regions within the first set of trenches along opposite side walls that do not extend outside of the trenches in the first direction but which leave spaces between the polysilicon regions in the first direction,
forming second polysilicon material in the spaces within the first set of trenches,
forming a second set of trenches into the substrate surface and first and second polysilicon material that are elongated in the first direction and spaced apart in the second direction, a depth of the second set of trenches being substantially equal to a depth of the first set of trenches, thereby to separate the side wall regions of the first polysilicon into individual floating gates,
forming conductive material in the second set of trenches between the floating gates in the second direction,
forming strips of conductive material elongated in the second direction and spaced apart in the first direction to pass over and contact the second polysilicon material in the first set of trenches and the conductive material in the second set of trenches, and
forming select gates over the substrate surface in between the first set of trenches in the first direction and connecting them to word lines elongated in the first direction and spaced apart in the second direction.