What is claimed is:
1. A method for managing a CAM (content addressable memory) look-up table using LPM (Longest Prefix Matching), the method comprising:
providing a pair of pointers per every band of data having the same prefix in length, wherein one of the pair of pointers stores the address of data having the lowest address in each band of data, and the other pointer of the pair of pointers stores the next higher address of data having the highest address in each band of data; and
making a space in which data is to be added in the CAM look-up table by moving data having the addresses stored in the pair of pointers provided per each band of data that has a shorter prefix length than the prefix length of the data to be added, when data is added to the CAM look-up table.
2. A method for managing a CAM look-up table using LPM wherein data having the longest prefix length is stored at the lowest address, the method comprising:
providing a pair of pointers per every band of data having the same prefix length, wherein one of the pair of pointers is a lower pointer which stores the address of data having the lowest address in each band of data, and the other pointer of the pair of pointers is an upper pointer which stores the next higher address of data having the highest address in each band of data; and
writing data having an address stored in the lower pointer provided per each band of data, which has a shorter prefix length than the prefix length of the data to be added, to the address stored in the upper pointer provided per each band of data, and writing the data to be added at the address stored in the upper pointer provided in the band of data having the same prefix length as the data to be added, in the case that data is added to the look-up table.
3. The method of claim 2 further comprising:
updating the addresses stored in the lower pointer and the upper pointer provided per each band of data which has a shorter prefix length than the prefix length of the data to be added so that the lower pointer and the upper pointer provided per each band of data may store the next higher addresses, and updating the addresses stored in the upper pointer provided per each band of data which has the same prefix length as the prefix length of the data to be added so that the upper pointer provided per said each band of data may store the next higher address.
4. A method for adding data to a CAM look-up table using LPM wherein data having the longest prefix length is stored at the lowest address, the method comprising:
providing a pair of pointers per every band of data having the same prefix in length, wherein one of the pair of pointers is a lower pointer which stores the address of data having the lowest address in each band of data, and the other pointer of the pair of pointers is an upper pointer which stores the next higher address of data having the highest address in each band of data;
receiving a command of adding data to the look-up table;
writing data having an address stored in the lower pointer provided per each band of data, which has a shorter prefix length than the prefix length of the data to be added, to the address stored in the upper pointer provided per said each band of data in order to make a space in which data is to be added in the CAM look-up table; and
writing the data, which is to be added, at the address stored in the upper pointer provided in the band of data having the same prefix length as the data to be added.
5. An apparatus for managing a CAM look-up table using the LPM, the apparatus comprising:
a CAM including a look-up table in which data having the longest prefix is stored at the lowest address;
a pointer storage unit including a pair of pointers per every band of data having the same prefix in length, wherein one of the pair of pointers is a lower pointer which stores the address of data having the lowest address in each band of data, and the other pointer of the pair of pointers is an upper pointer which stores the next higher address of data having the highest address in each band of data; and
a table managing unit for writing data having an address stored in the lower pointer provided per each band of data, which has a shorter prefix length than the prefix length of the data to be added, to the address stored in the upper pointer provided per each band of data, writing the data to be added, at the address stored in the upper pointer provided at the band of data having the same prefix length as the data to be added, and updating the addresses stored in the lower pointers and the upper pointers included in the pointer storage unit, in the case that data is added to the look-up table.
6. The apparatus of claim 5, wherein when updating the addresses stored in the lower pointer and the upper pointer included in the pointer storage unit, the table managing unit updates the addresses stored in the lower pointer and the upper pointer provided per each band of data, which has a shorter prefix length than the length of the prefix of the data to be added, so that the lower pointer and the upper pointer provided per said each band of data may store the next higher addresses, and updating the address stored in the upper pointer provided to the band of data which has the same prefix length as the prefix length of the data to be added, so that the upper pointer provided per said band of data may store the next higher address.
7. The apparatus of claim 5, wherein the upper and lower pointers are implemented as registers.
8. A computer-readable recording medium for recording a program that can implement a method of any one of claims 1 through 4 in a computer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A device comprising:
a substrate comprising at least one microelectronic andor nanoelectronic structure comprising at least one suspended portion,
a cover,
a fluid channel defined between said substrate and the cover, said fluid channel comprising two lateral walls and an upper wall connecting the two lateral walls formed by said cover and a lower wall formed by said substrate and at least two openings in order to provide a circulation in said channel, said microelectronic andor nanoelectronic structure being located inside the fluid channel,
an intermediate layer comprising a face in contact with base faces of said lateral walls, said face of the intermediate layer having an aptitude for sealing with the base faces,
at least one electrical connection line extending between said microelectronic andor nanoelectronic structure and the outside of the fluid channel, said connection line being carried out on the substrate and passing under one of the lateral walls, said at least one electrical connection line being at least partially covered by said intermediate layer at least immediately above the base face of said lateral wall, said lateral walls being sealingly fixed on said substrate by a sealing mechanism on said intermediate layer.
2. The device according to claim 1, comprising a functionalization layer encapsulating at least one portion of the suspended portion of the microelectronic andor nanoelectronic structure.
3. The device according to claim 2, wherein the functionalization layer comprises one or several materials chosen from among organic or inorganic materials, polymers, oxides, semiconductors.
4. The device according to claim 1, wherein the at least one electrical connection line comprises at least one pair of connection lines extending laterally on either side of the microelectronic andor nanoelectronic structure and each passing under a lateral wall.
5. The device according to claim 1, wherein the intermediate layer covers, in the fluid channel, the entire microelectronic andor nanoelectronic structure except for its suspended portion.
6. The device according to claim 1, wherein the intermediate layer comprises an electrical insulating material, such as silicon oxide, or a silicon nitride.
7. The device according to claim 1, comprising electrical connection lines and contact pads, said contact pads being located outside of the fluid channel, said connection lines extending between the microelectronic andor nanoelectronic structure and the contact pads.
8. The device according to claim 1, wherein the electrical connection lines comprise several levels of metallisation at least inside the fluid channel.
9. The device according to claim 1, comprising a dry film for sealing inserted between the intermediate layer and the base faces of the lateral walls of the cover.
10. The device according to claim 9, wherein the dry film for sealing is structured into several beads on interfaces between the intermediate layer and the base faces of the lateral walls.
11. The device according to claim 1, comprising at least one layer of material inserted between the intermediate layer and the base faces of the lateral walls creating a eutectic sealing or by thermo-compression, or by screen printing or wherein the sealing is a molecular sealing or wherein the sealing is made by glass frit.
12. The device according to claim 1, wherein the intermediate layer comprises a first layer of electrical insulating material in contact with the electrical connection line and a second layer deposited onto the first layer, said second layer being of a material such that it is little or not sensitive to a step of releasing the microelectronic andor nanoelectronic structure.
13. The device according to claim 12, wherein the second layer is made of Si, silicon nitride, metal or hafnium oxide.
14. The device according to claim 1, wherein the channel forms a gas chromatography microcolumn.
15. A method of carrying out at least one device according to claim 1, comprising the steps of:
a) carrying out the microelectronic andor nanoelectronic structure on a substrate and of at least one connection line,
b) forming of the intermediate layer is such a way that it has a substantially planar free face having an opening above said at least suspended portion
c) carrying out of a cover substrate comprising a fluid channel,
d) sealing of the cover substrate on the intermediate layer in such a way that the fluid channel is arranged facing the microelectronic andor nanoelectronic structure.
16. The method according to claim 15, comprising a step of carrying out a functionalization layer inside the fluid channel on the microelectronic andor nanoelectronic structure andor on the walls of the cover andor on the intermediate layer, said step being carried out before the sealing.
17. The method of carrying out according to claim 15, comprising after the step b), a step of releasing said microelectronic andor nanoelectronic structure.
18. The method of carrying out according to claim 15, wherein the step of sealing using a dry film, the method for carrying out comprises the sub-steps of:
rolling of dry film on the base faces of the walls of the cover,
structuring of the dry film,
coming closer together of the cover and of the substrate comprising the microelectronic andor nanoelectronic structure,
application of a pressure in such a way as to crush the dry film.
19. The method of carrying out according to claim 15, wherein the sealing is a eutectic sealing or by thermo-compression, or by molecular sealing or by screen printing.
20. The method of carrying out according to claim 15, wherein the carrying out of the intermediate layer takes place by deposit of a first layer of electrical insulating material and of deposit of a second layer on the first layer.
21. The method of carrying out according to claim 15, wherein several devices are carried out simultaneously, said substrate comprising several microelectronic andor nanoelectronic structures and the cover substrate comprising several covers, with the covers being sealed simultaneously on the substrate comprising the microelectronic andor nanoelectronic structures, in such a way that a fluid channel of a device can communicate or not with the fluid channel of other devices.
22. The method of carrying out according to claim 21, comprising the steps of:
carrying out pre-cuts in a direction perpendicular to the fluid channels in the cover substrate and in the substrate bearing the microelectronic structures andor
carrying out cuts or pre-cuts in a direction parallel to the fluid channels in the substrate bearing the microelectronic andor nanoelectronic structures,
separating devices.
23. The method of carrying out according to claim 22, wherein the separation of the devices is carried by cleavage.
24. The method of carrying out according to claim 22, wherein the cover substrate comprising cavities formed beforehand between the channels wherein are located contact pads after sealing, the method further comprises a step of cutting the cover substrate in order to open said cavities.
25. The method of carrying out according to claim 23, wherein the cover substrate comprising cavities formed beforehand between the channels wherein are located contact pads after sealing, the method further comprises a step of cutting the cover substrate in order to open said cavities.
26. The method of carrying out according to claim 24, wherein a functionalization layer has been formed on said microelectronic andor nanoelectronic structure and on the contact pads before the sealing, said method comprising the step of removing by etching of the functionalisation layer on the contact pads after sealing and opening of the cavities in the cover, said covers forming masks to said etching for the microelectronic andor nanoelectronic structures.
27. The method of carrying out according to claim 25, wherein a functionalization layer has been formed on said microelectronic andor nanoelectronic structure and on the contact pads before the sealing, said method comprising the step of removing by etching of the functionalization layer on the contact pads after sealing and opening of the cavities in the cover, said covers forming masks to said etching for the microelectronic andor nanoelectronic structures.
28. A method of carrying out at least one device according to claim 1, comprising the steps of:
a) carrying out the microelectronic andor nanoelectronic structure on a substrate and of at least one connection line,
b) forming of the intermediate layer in such a way that it has a substantially planar free face having an opening above said at least suspended portion
c) carrying out of a cover substrate comprising a fluid channel,
d) sealing of the cover substrate on the intermediate layer in such a way that the fluid channel is arranged facing the microelectronic andor nanoelectronic structure, the method also comprising a step of carrying out a functionalization layer inside the fluid channel on the microelectronic andor nanoelectronic structure andor on the walls of the cover andor on the intermediate layer, said step being carried out before the sealing.