1. A method of determining access node capacity, comprising:
determining a first throughput of information received from a first access node at an application running on a wireless device;
determining a second throughput of information received from a second access node at the application running on the wireless device, wherein the first access node does not receive capacity information from the second access node;
identifying unique modulation and coding schemes (MCS’) assigned to the wireless device for communication with the respective first and second access nodes;
estimating a number of free physical resource blocks per frame of the first access node and of the second access node based on the respective first and second throughputs of information and based on the identified MCS’ assigned to the wireless device for communication with each of the first and second access nodes; and,
based on the estimated number of free physical resource blocks per frame of the first access node and of the second access node, instructing the wireless device to change from communicating with the first access node to communicating with the second access node.
2. The method of claim 1, wherein the first throughput of information received at the application running on the wireless device is associated with a lowest traffic class indicator from among a plurality of traffic class indicators.
3. The method of claim 1, further comprising:
changing the MCS assigned to the wireless device for communication with the first access node to a second MCS;
determining a third throughput of the information received from the first access node at the application running on the wireless device; and
estimating, based on the third determined throughput of information, a second number of free physical resource blocks per frame of the first access node based on the second MCS and the third throughput.
4. The method of claim 3, further comprising determining a total number of free physical resource blocks per frame of the first access node based on the estimated number of free physical resource blocks per frame of the first access node.
5. The method of claim 1, further comprising:
instructing the wireless device to change from communicating with the first access node to the second access node when the estimated number of free physical resource blocks per frame of the first access node and of the second access node indicate that the second access node has a greater capacity than the first access node.
6. The method of claim 1, wherein the second throughput of information received from the second access node at the application running on the wireless device comprises test data sent from the first access node to the wireless device.
7. A method of determining access node capacity, comprising:
determining a first throughput of information received from a first access node at an application running on a first wireless device;
determining a second throughput of information received from a second access node at an application running on a second wireless device, wherein the first access node does not receive capacity information from the second access node;
identifying a modulation and coding scheme (MCS) assigned to the first wireless device for communication with the first access node;
identifying a MCS assigned to the second wireless device for communication with second access node;
estimating a number of free physical resource blocks per frame of the first access node based on the first throughput of information and the MCS assigned to the first wireless device, and a number of free physical resource blocks per frame of the second access node based on the second throughput of information and the MCS assigned to the second wireless device; and
based on the estimated number of free physical resource blocks per frame of the respective first and second access nodes, instructing the first wireless device to change from communicating with the first access node to communicating with the second access node.
8. The method of claim 7, further comprising:
instructing the first wireless device to change from communicating with the first access node to communicating with the second access node when the estimated number of free physical resource blocks per frame of the first access node and of the second access node indicate that the second access node has a greater capacity than the first access node.
9. The method of claim 7, wherein the first throughput of information received from the first access node at the first wireless device and the second throughput of information received from the second access node at the second wireless device are each associated with a lowest traffic class indicator from among a plurality of traffic class indicators.
10. The method of claim 7, further comprising:
determining a third throughput of information received from the first access node at an application running on a third wireless device;
identifying a MCS assigned to the third wireless device for communication with the first access node, wherein the MCS assigned to the third wireless device is different than the MCS assigned to the first wireless device;
determining a fourth throughput of information received from the second access node at an application running on a fourth wireless device;
identifying a MCS assigned to the fourth wireless device for communication with the second access node, wherein the MCS assigned to the fourth wireless device is different than the MCS assigned to the second wireless device;
estimating the number of free physical resource blocks per frame of the first access node based on the first throughput of information received at the first wireless device, the MCS assigned to the first wireless device, the third throughput of information received at the third wireless device, and the MCS assigned to the third wireless device; and
estimating the number of free physical resource blocks per frame of the second access node based on the second throughput of information received at the second wireless device, the MCS assigned to the second wireless device, the fourth throughput of information received at the fourth wireless device, and the MCS assigned to the fourth wireless device.
11. The method of claim 7, further comprising:
determining a third throughput of information received from a third access node at an application running on a third wireless device;
identifying a MCS assigned to the third wireless device for communication with third access node; and
estimating a number of free physical resource blocks per frame of the third access node based on the third throughput of information and the MCS assigned to the third wireless device, and
wherein the first and second access nodes do not receive capacity information from the third access node.
12. The method of claim 11, further comprising:
instructing the first wireless device to change from communicating with the first access node to communicating with the third access node based on the estimated number of free physical resource blocks per frame of the first access node, the second access node, and the third access node.
13. The method of claim 11 further comprising:
instructing the first wireless device to change from communicating with the first access node access to communicating with the third access node when the estimated number of free physical resource blocks per frame of the first access node, the second access node, and the third access node indicate that the third access node has a greater capacity than the first and second access nodes.
14. The method of claim 12, wherein the first throughput of information received from the first access node, the second throughput of information received from the second access node, and the third throughput of information received from the third access node are each associated with a lowest traffic class indicator from among a plurality of traffic class indicators.
15. The method of claim 11, further comprising:
estimating the number of free physical resource blocks per frame of the first access node, the second access node, and the third access node at a predetermined time based on historical capacity information of the first access node.
16. The method of claim 11, further comprising:
estimating the number of free physical resource blocks per frame of the first access node, the second access node, and third access node at a predetermined time based on historical capacity information of the first access node, the second access node, and third access node.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit device comprising:
a memory cell consisting essentially of an electrically floating body transistor, wherein the electrically floating body transistor comprises:
a source region;
a drain region;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and
a gate disposed over the body region;
circuitry, coupled to the memory cell, to write a data state into the memory cell and to read the data state of the memory cell;
wherein, in response to write control signals applied to the electrically floating body transistor, the electrically floating body transistor stores a charge which is representative of a data state of the memory cell in the body region of the electrically floating body transistor; and
wherein, in response to read control signals applied to the electrically floating body transistor, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the circuitry determines the data state of the memory cell based on a signal which is representative of the bipolar transistor current of the electrically floating body transistor.
2. The integrated circuit device of claim 1 wherein electrically floating body transistor is an N-channel type transistor or a P-channel type transistor.
3. The integrated circuit device of claim 1 wherein electrically floating body transistor is non-symmetrical.
4. The integrated circuit device of claim 1 wherein the read control signals include signals applied to the gate, source region, and drain region to cause, force andor induce the bipolar transistor current which is representative of the data state of the memory cell.
5. The integrated circuit device of claim 4 wherein the read control signals include a positive voltage pulse which is applied to the drain region of the electrically floating body transistor and wherein the circuitry is connected to the drain region via a bit line.
6. The integrated circuit device of claim 4 wherein the read control signals include a negative voltage pulse which is applied to the drain region of the electrically floating body transistor and wherein the circuitry is connected to the drain region via a bit line.
7. The integrated circuit of claim 1 wherein, if the memory cell stores a logic low, the electrically floating body transistor, in response to the read control signals applied thereto, generates a bipolar transistor current equal to or substantially equal to zero.
8. The integrated circuit of claim 1 wherein the signal which is representative of the bipolar transistor current of the electrically floating body transistor is a voltage amplitude.
9. An integrated circuit device comprising:
a memory cell consisting essentially of an electrically floating body transistor, wherein the electrically floating body transistor comprises of:
a first region having impurities to provide a first conductivity type;
a second region having impurities to provide the first conductivity type;
a body region disposed between the first region and the second region wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type; and
a gate disposed over the body region;
circuitry, coupled to the memory cell, to write a data state into the memory cell and to read the data state of the memory cell;
wherein, in response to the write control signals applied to the electrically floating body transistor, the electrically floating body transistor stores a charge which is representative of the data state in the body region of the electrically floating body transistor; and
wherein, in response to the read control signals, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the circuitry determines the data state of the memory cell based on a signal which is representative of the bipolar transistor current of the electrically floating body transistor.
10. The integrated circuit device of claim 9 wherein electrically floating body transistor is an N-channel type transistor or a P-channel type transistor.
11. The integrated circuit device of claim 9 wherein electrically floating body transistor is non-symmetrical.
12. The integrated circuit device of claim 9 wherein the read control signals include signals applied to the gate, first region, and second region to cause, force andor induce the bipolar transistor current which is representative of the data state of the memory cell.
13. The integrated circuit device of claim 12 wherein the read control signals include a positive voltage pulse which is applied to the second region of the electrically floating body transistor and wherein circuitry is connected to the second region via a bit line.
14. The integrated circuit device of claim 12 wherein the read control signals include a negative voltage pulse which is applied to the second region of the electrically floating body transistor and wherein the circuitry is connected to the second region via a bit line.
15. The integrated circuit of claim 9 wherein, if the memory cell stores a logic low, the electrically floating body transistor, in response to the read control signals applied thereto, generates a bipolar transistor current equal to or substantially equal to zero.
16. The integrated circuit of claim 9 wherein the signal which is representative of the bipolar transistor current of the electrically floating body transistor is a voltage amplitude.
17. An integrated circuit device comprising:
a memory cell consisting essentially of an electrically floating body transistor, wherein the electrically floating body transistor is disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the electrically floating body transistor comprises:
a source region having impurities to provide a first conductivity type;
a drain region having impurities to provide the first conductivity type,
a body region disposed between the source region, the drain region and the insulating region or layer of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type; and
a gate spaced apart from the body region;
circuitry, coupled to the memory cell, to (i) read a data state of the memory cell and (ii) generate and apply read control signals to the electrically floating body transistor; and
wherein, in response to the read control signals, the electrically floating body transistor generates a bipolar transistor current which Is representative of the data state of the memory cell and wherein the circuitry determines the data state of the memory cell based on a signal which is representative of the bipolar transistor current of the electrically floating body transistor.
18. The integrated circuit device of claim 17 wherein electrically floating body transistor is an N-channel type transistor or a P-channel type transistor.
19. The integrated circuit device of claim 17 wherein electrically floating body transistor is non-symmetrical.
20. The integrated circuit device of claim 17 wherein the read control signals include signals applied to the gate, source region, and drain region to cause, force andor induce the bipolar transistor current which is representative of the data state of the memory cell.
21. The integrated circuit device of claim 20 wherein the read control signals include a positive voltage pulse which is applied to the drain region of the electrically floating body transistor and wherein the circuitry is connected to the drain region via a bit line.
22. The integrated circuit device of claim 20 wherein the read control signals include a negative voltage pulse which is applied to the drain region of the electrically floating body transistor and wherein the circuitry is connected to the drain region via a bit line.
23. The integrated circuit of claim 17 wherein, if the memory cell stores a logic low, the electrically floating body transistor, in response to the read control signals applied thereto, generates a bipolar transistor current equal to or substantially equal to zero.
24. The integrated circuit of claim 17 wherein the signal which is representative of the bipolar transistor current of the electrically floating body transistor is a voltage amplitude.
25. A method of operating an integrated circuit device having a memory cell comprising an electrically floating body transistor, wherein the electrically floating body transistor comprises: (i) a source region, (ii) a drain region, (iii) a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and (iv) a gate disposed over the body region, the method comprises:
applying read control signals to the electrically floating body transistor of the memory cell, wherein, in response to the read control signals, the electrically floating body transistor generates a bipolar transistor current which is representative of a data state of stored in the memory cell;
generating a voltage, having an amplitude, using the bipolar transistor current;
determining the data state of the memory cell based on the amplitude of the voltage which is representative of an amount of the bipolar transistor current generated by the electrically floating body transistor; and
outputting the data state of the memory cell.
26. The method of claim 25 further including applying write control signals to the electrically floating body transistor of the memory cell, wherein in response to the write control signals the electrically floating body transistor stores a charge which is representative of a data state in the body region of the electrically floating body transistor.
27. The method of claim 25 wherein the read control signals include a positive voltage pulse which is applied to the drain region of the electrically floating body transistor.
28. The method of claim 25 wherein the read control signals include a negative voltage pulse which is applied to the drain region of the electrically floating body transistor.
29. The method of claim 25 wherein, if the memory cell stores a logic low, the electrically floating body transistor, in response to the read control signals, generates a bipolar transistor current equal to or substantially equal to zero.
30. A method of operating an integrated circuit device having a memory cell comprising an electrically floating body transistor, wherein the electrically floating body transistor comprises: (i) a source region, (ii) a drain region, (iii) a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and (iv) a gate disposed over the body region, the method comprises:
applying write control signals to the electrically floating body transistor of the memory cell, wherein, in response to the write control signals, the electrically floating body transistor stores a charge which is representative of a data state in the body region of the electrically floating body transistor; and
applying read control signals to the electrically floating body transistor of the memory cell, wherein, in response to the read control signals, the electrically floating body transistor generates a bipolar transistor current which is representative of a data state of stored in the memory cell.
31. The method of claim 30 wherein the read control signals include a positive or negative voltage pulse which is applied to the drain region of the electrically floating body transistor.
32. The method of claim 30 further including:
generating a voltage, having an amplitude, using the bipolar transistor current generated by the electrically floating body transistor in response to the read control signals;
determining the data state of the memory cell based on the amplitude of the voltage; and
outputting the data state of the memory cell.
33. The method of claim 32 wherein, if the memory cell stores a logic low, the electrically floating body transistor, in response to the read control signals, generates a bipolar transistor current equal to or substantially equal to zero.