1. A system suitable for determining bus frequency, comprising:
a bus device suitable for performing an operation; and
a processor communicatively coupled to the bus device utilizing a bus, wherein the processor is capable of starting a timer, initiating the bus device to perform a number of operations, receiving an indication that the number of operations were completed by the bus device, stopping the timer when the indication is received and computing a bus clock frequency based upon time taken to complete the number of operations as indicated by the timer and the number of operations performed by the bus device.
2. The system as described in claim 1, wherein the bus clock frequency is computed by the following, the bus clock frequency is equal to X divided by time, wherein X is equal the number of operations performed, and time is equal to time needed to perform the X number of operations.
3. The system as described in claim 1, wherein an operation takes more than one bus clock to perform, the bus clock frequency is equal to (K*X)time, wherein K is equal to the number of bus clocks needed to perform the operation, X is equal the number of operations performed, and time is equal to time needed to perform the X number of operations.
4. The system as described in claim 1, wherein the operation is a no operation (NOP).
5. The system as described in claim 1, wherein the processor is a central processing unit (CPU).
6. The system as described in claim 1, wherein the bus includes at least one of Industry Standard Architecture (ISA), Extended Industry Standard Architecture (EISA), Micro Channel Architecture, Peripheral Component Interconnect (PCI), and Peripheral Component Interconnect-X (PCI-X).
7. A method of determining bus frequency, comprising:
starting a timer by a processor;
initiating a bus device communicatively coupled to the processor over a bus, wherein the bus device is initiated to perform a number of operations;
receiving an indication by the processor, the indication suitable for indicating that the number of operations were performed by the bus device;
stopping the timer by the processor in response to the received indication; and
computing a bus clock frequency based upon time taken to complete the number of operations as indicated by the timer and the number of operations performed by the bus device.
8. The method as described in claim 7, wherein the bus clock frequency is computed by the following, the bus clock frequency is equal to X divided by time, wherein X is equal the number of operations performed, and time is equal to time needed to perform the X number of operations.
9. The method as described in claim 7, wherein an operation takes more than one bus clock to perform, the bus clock frequency is equal to (K*X)time, wherein K is equal to the number of bus clocks needed to perform the operation, X is equal the number of operations performed, and time is equal to time needed to perform the X number of operations.
10. The method as described in claim 7, wherein the operation is a no operation (NOP).
11. The method as described in claim 7, wherein the processor is a central processing unit (CPU).
12. The method as described in claim 7, wherein the bus includes at least one of Industry Standard Architecture (ISA), Extended Industry Standard Architecture (EISA), Micro Channel Architecture, Peripheral Component Interconnect (PCI), and Peripheral Component Interconnect-X (PCI-X).
13. A method of determining bus frequency, comprising:
initiating a bus device communicatively coupled to a processor over a bus, wherein the bus device is initiated to perform a number of operations;
receiving an indication by the processor, the indication suitable for indicating that the number of operations were performed by the bus device; and
computing a bus clock frequency based upon time taken to complete the number of operations performed by the bus device.
14. The method as described in claim 13, wherein the time is measured utilizing a timer accessible by the processor.
15. The method as described in claim 13, wherein the timer is included with the processor.
16. The method as described in claim 13, wherein the bus clock frequency is computed by the following, the bus clock frequency is equal to X divided by time, wherein X is equal the number of operations performed, and time is equal to time needed to perform the X number of operations.
17. The method as described in claim 13, wherein an operation takes more than one bus clock to perform, the bus clock frequency is equal to (K*X)time, wherein K is equal to the number of bus clocks needed to perform the operation, X is equal the number of operations performed, and time is equal to time needed to perform the X number of operations.
18. The method as described in claim 13, wherein the operation is a no operation (NOP).
19. The method as described in claim 13, wherein the processor is a central processing unit (CPU).
20. The method as described in claim 13, wherein the bus includes at least one of Industry Standard Architecture (ISA), Extended Industry Standard Architecture (EISA), Micro Channel Architecture, Peripheral Component Interconnect (PCI), and Peripheral Component Interconnect-X (PCI-X).
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A circuit arrangement, comprising:
a memory unit operable in a low-power operating mode and in a normal-power operating mode;
a setting unit for setting the operating mode of the memory unit;
a detector unit for detecting an access operation to the memory unit;
a control unit for controlling the setting unit on the basis of the detection result from the detector unit; wherein the detector unit and the control unit are hardware components;
a processor which executes software for configuring at least one of the detector unit and the control unit;
a first bus connecting the processor and the memory unit; and
an additional processor which is connected to the setting unit via a second bus, with data interchange not being possible between the first and second buses.
2. The circuit arrangement of claim 1, wherein the detector unit is configured to detect a selection signal used to select the memory unit in the event of an access operation.
3. The circuit arrangement of claim 2, wherein the detector unit is configured to detect readwrite signals related to the access operation to the memory unit, and wherein the control unit controls the setting unit on the basis of the readwrite signals.
4. The circuit arrangement of claim 1, wherein the detector unit has an address comparator configured to compare at least portions of addresses of an access operation with at least portions of predefined addresses and, on the basis of the comparison, detect an access operation to the memory unit.
5. The circuit arrangement of claim 4, wherein the address comparator has registers storing the predefined addresses.
6. The circuit arrangement of claim 1, wherein the control unit comprises a measuring unit configured to measure an elapsed time period between the access operation to the memory unit and a next access operation.
7. The circuit arrangement of claim 6, wherein the control unit is configured to signal the setting unit to change the operating mode of the memory unit to the low-power operating mode from the normal-power operating mode in the event the elapsed time period is longer than a prescribed time period.
8. The circuit arrangement of claim 7, wherein the control unit has registers storing the prescribed time period.
9. The circuit arrangement of claim 8, wherein the prescribed time period is stored in the registers by the software which is being executed on the processor.
10. The circuit arrangement of claim 1, further comprising an interruption unit configured to interrupt the access operation to the memory unit in the event the memory unit is in the low-power operating mode at the time of the access operation.
11. The circuit arrangement of claim 1, further comprising a unit for selectively activating and deactivating the control unit.
12. The circuit arrangement of claim 1, wherein the detector unit and the control unit have a supply voltage applied to them during the low-power operating mode of the memory unit.
13. The circuit arrangement of claim 1, wherein the memory unit is operable in at least two different low-power operating modes, and the control unit selects the operating mode of the memory unit from the at least two low-power operating modes and the normal-power operating mode.
14. The circuit arrangement of claim 1, further comprising:
an additional memory unit operable in a low-power operating mode and in a normal-power operating mode;
an additional setting unit for setting the operating mode of the further memory unit;
an additional detector unit for detecting an access operation to the additional memory unit; and
an additional control unit for controlling the additional setting unit on the basis of the detection result from the additional detector unit, wherein the additional detector unit and the additional control unit are hardware components.
15. The circuit arrangement of claim 1, wherein the memory unit is one of a read-only memory (ROM), static random access memory (SRAM) and a dynamic random access memory (DRAM).