1. A system for measuring the radiation diagram of a transmitting antenna, the system including:
(a) a receiver device provided with at least one fixed receiving antenna for picking up an electromagnetic field to be measured and generated by a transmitting antenna to be belonging to an electronic device;
(b) a positioning device, on which a support element for the electronic device is placed, wherein the positioning device includes:
i, means for driving the support element in rotation with the electronic device;
ii, detection means for detecting position or orientation of the transmitting antenna; and
iii, a data processing station for processing data supplied by the detection means and by the receiver device, wherein
the support element is a spherical hollow element that houses the electronic device and the transmitting antenna, and the spherical element is held on the positioning device by gravity on three points of first support, wherein one point of first support is formed by a drive member in contact with an external surface of the spherical element so as to rotate the spherical element randomly in every direction on the positioning device, and the other two points of first support of the positioning device are each formed by a ball and socket joint, wherein the ball is placed to rotate freely in an end housing of the ball and socket joint so that one portion of the ball emerges through an aperture in the housing to come into contact with the external surface of the spherical element.
2. The measuring system according to claim 1, wherein the drive member is a wheel that comes into contact with the external surface of the spherical element to drive said spherical element in rotation, wherein a rotating axle of the wheel is mounted at an end of a second support that can rotate along a second axle, and the second axle passes through a point of contact of the wheel on the external surface of the spherical element and the center of the spherical element so as to impose a random rotation on the spherical element via the wheel, in every direction.
3. The measuring system according to claim 1, wherein a portion of the ball and socket joint that houses the ball is a nozzle, for bringing compressed air, so that the ball is held in the housing on an air cushion.
4. The measuring system according to claim 1, wherein the detection means include a digital camera that is connected to the data processing station, and figures or references are distributed over the external surface of the spherical element to enable the digital camera, associated with the data processing station, to determine position or orientation of the transmitting antenna when placed in proximity to the center of the spherical element.
5. The measuring system according to claim 4, wherein the figures or references are formed by circular barcodes, and each circular barcode defines a precise position of the spherical element on the positioning device.
6. The measuring system according to claim 5, wherein fourteen different circular barcodes are uniformly distributed over the external surface of the spherical element, wherein each circular barcode is encoded in four bits, and an external delimiting bit of a different colour to a first colour of the external surface of the spherical element so as to define an edge of each figure.
7. The measuring system according to claim 4, further including a lighting device for lighting, in a uniform manner, a portion of the external surface of the spherical element that is visible to the digital camera.
8. The measuring system according to claim 7, wherein the lighting device includes a set of optical fibers guiding light generated by a light source distant from the spherical element so as to provide a homogenous light beam to improve an image of the spherical element, with the various figures visible, captured by the digital camera.
9. The measuring system according to claim 8, wherein the set of optical fibers is divided into several sub-sets of optical fibers, wherein ends of the optical fibers of each sub-set in proximity to the spherical element are secured in plastic studs on a lighting structure.
10. The measuring system according to claim 9, wherein the lighting structure is made of a non-metal material and forms a ring on which a plurality of plastic studs are arranged over the entire periphery of the ring and equidistant from each other for the optical fiber ends of the sub-sets, and the ring is placed in front of the spherical element on at side of the digital camera without obstructing the digital camera’s view of the spherical element, and the ends of the optical fibers of each sub-set are oriented so as to direct light beams in the direction of the center of the spherical element.
11. The measuring system according to claim 9, wherein the number of optical fibers per sub-set is at least two optical fibers and whose ends are secured in one of the plastic studs and are equidistant from each other, and are arranged in the form of equilateral triangles.
12. The measuring system according to claim 10, wherein the number of optical fibers per sub-set is at least two optical fibers and whose ends are secured in one of the plastic studs and are equidistant from each other, and are arranged in the form of equilateral triangles.
13. The measuring system according to claim 10, wherein the plurality of plastic studs consists of six plastic studs.
14. The measuring system according to claim 9, wherein the number of optical fibers per sub-set is six optical fibers whose ends are secured in one of the plastic studs and are equidistant from each other, and are arranged in the form of equilateral triangles.
15. The measuring system according to claim 10, wherein the number of optical fibers per sub-set is six optical fibers whose ends are secured in one of the plastic studs and are equidistant from each other, and are arranged in the form of equilateral triangles.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A memory device comprising:
a memory cell array comprising a plurality of memory cells and cell select circuitry configured to selectively connect the plurality of memory cells to a data line;
a bias circuit operative to charge the data line to a bias voltage responsive to a bias enable signal; and
a sense amplifier circuit having an input coupled to the data line and including an output buffer, the sense amplifier circuit operative to drive the output buffer according to a voltage on the data line responsive to a sense enable signal to thereby generate a sense amplifier output signal indicative of a state of a memory cell connected to the data line.
2. A device according to claim 1, wherein the bias circuit comprises:
a buffer having an input coupled to the data line and operative to be enabled and disabled responsive to the bias enable signal;
a first transistor having a drain coupled to the input of the buffer, a source coupled to a power supply node and a gate coupled to an output of the buffer; and
a second transistor having a source coupled to the power supply node, a drain coupled to the output of the buffer, and a gate coupled to the bias enable signal.
3. A device according to claim 2, wherein the first and second transistors comprise respective PMOS transistors.
4. A device according to claim 1, wherein the sense amplifier circuit comprises:
first and second complementary transistors coupled in series between the data line and the power supply node and coupled to an input of the output buffer at a junction of the first and second transistors; and
a sense enable circuit coupled to the data line and to a gate of the first transistor, the sense enable circuit operative to drive the gate of the first transistor responsive to the sense amplifier enable signal.
5. A device according to claim 4, wherein the sense enable circuit comprises:
an inverter having an input coupled to the data line and an output coupled to the gate of the first transistor, the inverter operative to be enabled and disabled responsive to the sense amplifier; and
a third transistor having a drain coupled to an output of the inverter, a source coupled to a ground node, and a gate that receives the sense amplifier enable signal.
6. A device according to claim 5, wherein the first transistor comprises an NMOS transistor having a source coupled to the data line, and wherein the second transistor comprises a PMOS transistor having a drain coupled to a drain of the NMOS transistor and a source coupled to the power supply node.
7. A device according to claim 1:
wherein the data line is coupled to an input of the buffer;
wherein the output buffer comprises an inverter operative to be enabled and disabled responsive to the sense amplifier enable signal; and
wherein the sense amplifier circuit comprises a transistor coupled between the data line and the power supply node and having a gate that receives the sense amplifier enable signal.
8. A device according to claim 1, wherein the cell select circuitry is configured to selectively couple the memory cells to a plurality of bit lines responsive to signals on word lines, and wherein the cell select circuitry includes a gate circuit that selectively couples the bit lines to the data line responsive to a plurality of column select signals.
9. A memory device comprising:
a memory cell array with a plurality of memory cells connected to a plurality of word lines and operative to be selectively connnected to a plurality of bit lines responsive to signals on the word lines;
a pre-discharge circuit that predischarges the plurality of bit lines during a pre-discharge operation;
a data input and output gate circuit that transmits data between the plurality of bit lines and a plurality of data lines during a read operation; and
a sense amplifier including a bias circuit that biases the data lines to a bias voltage level in response to a bias control signal during the read operation, and an amplifier circuit that detects and amplifies voltage changes on the plurality of data lines and that responsively generates a sense output signal subject to a sense amplifier enable signal during the read operation.
10. A device according to claim 9, wherein the bias circuit comprises:
a first transistor connected between a power supply voltage and the data line;
a second transistor being turned on in response to the bias control signal for turning off the first transistor during the pre-discharge operation, and being turned on when the sense amplifier enable signal is enabled during the read operation; and
a first buffer being enabled in response to the bias control signal for buffering a voltage signal of the data line during the read operation, and being disabled when the sense amplifier enable signal is enabled during the read operation.
11. A device according to claim 10, wherein the first and second transistors comprise respective PMOS transistors.
12. A device according to claim 10, wherein the first buffer generates a signal with a power supply voltage when a voltage of the data line is greater than the bias voltage, and generates the signal with a ground voltage when the voltage of the data line is lower than the bias voltage.
13. A device according to claim 9, wherein the sense amplifier circuit comprises:
a third transistor that is connected between a power supply voltage and a first node and that supplies a current to the first node;
an inverter operative to be enabled in response to the sense amplifier enable signal and that inverts a voltage level of the data line and transmits the inverted voltage level to a second node;
a fourth transistor connected between the second node and a ground voltage and operative to be turned off in response to the sense amplifier enable signal during the read operation;
a fifth transistor connected between the first node and the data line and operative to be turned on in response to a voltage signal of the second node to let a current flow from the first node to the data line; and
a second buffer operative to be enabled in response to the sense amplifier enable signal and to buffer a signal of the first node and responsively generate the sense output signal.
14. A device according to claim 13, wherein a transconductance of the fifth transistor is greater than a transconductance of the third transistor.
15. A device according to claim 13, wherein the third transistor is a PMOS transistor.
16. A device according to claim 13, wherein the fifth and fourth transistors comprise respective NMOS transistors.
17. A device according to claim 13, wherein the inverter generates a signal with a ground voltage when a voltage of the data line is greater than the bias voltage, and generates the signal with a power supply voltage when a voltage of the data line is lower than the bias voltage.
18. A device according to claim 9, wherein the sense amplifier circuit comprises:
a third transistor that is connected between a power supply voltage and a first node and that supplies a current to the first node;
a fourth transistor that is connected between the first node and the data line and that supplies a current to the data line by being turned on in response to the sense amplifier enable signal; and
a second buffer operative to be enabled in response to the sense amplifier enable signal and to buffer a voltage signal of the data line to generate the sense output signal.
19. A device according to claim 18, wherein the third and fourth transistors comprise respective PMOS transistors.
20. A device according to claim 18, wherein the second buffer generates the sense output signal with a ground voltage when a voltage level of the data line is lower than that of the bias voltage, and generates the sense output signal with a power supply voltage when a voltage level of the data line is higher than that of the bias voltage.
21. A sense amplifier comprising:
a bias circuit that biases a sense input signal terminal to a bias voltage level in response to a bias control signal; and
a sense amplifier circuit that generates a sense output signal by detecting and amplifying a change of the bias voltage level of the sense input signal terminal in response to a sense amplifier enable signal.
22. A sense amplifier according to claim 21, wherein the bias circuit comprises:
a first transistor connected between a power supply voltage and the sense input signal terminal;
a second transistor that turns off the first transistor by being turned on in response to the bias control signal and by being turned on when the sense amplifier enable signal is enabled; and
a first buffer operative to be enabled in response to the bias control signal and to buffer a voltage of the sense input signal terminal, and to be disabled when the sense amplifier enable signal is enabled.
23. A sense amplifier according to claim 22, wherein the first and second transistors comprise respective PMOS transistors.
24. A sense amplifier according to claim 22, wherein the first buffer generates a signal with a power supply voltage if a voltage of the sense input signal terminal is greater than the bias voltage and generates the signal with a ground voltage if a voltage of the sense input signal terminal is less than the bias voltage.
25. A sense amplifier according to claim 21, wherein the sense amplifier circuit comprises:
a third transistor that is connected between a power supply voltage and a first node and that supplies a current to the first node;
an inverter operative to be enabled in response to the sense amplifier enable signal and to invert a voltage level of the data line and to transmit the inverted voltage level to a second node;
a fourth transistor connected between the second node and a ground voltage and operative to be turned off in response to the sense amplifier enable signal;
a fifth transistor connected between the first node and the sense input signal terminal and operative to be turned on in response to a signal of the second node to let a current flow from the first node to the sense input signal terminal; and
a second buffer operative to be enabled in response to the sense amplifier enable signal and to buffer a signal of the first node to generate the sense output signal.
26. A sense amplifier according to claim 25, wherein a transconductance of the fifth transistor is greater than a transconductance of the third transistor.
27. A sense amplifier according to claim 26, wherein the third transistor is a PMOS transistor.
28. A sense amplifier according to claim 25, wherein the fifth and fourth transistors comprise respective NMOS transistors.
29. A sense amplifier according to claim 25, wherein the inverter generates a signal with a ground voltage when a voltage of the sense input signal terminal is greater than the bias voltage, and generates the signal with a power supply voltage when a voltage of the sense input signal terminal is lower than the bias voltage.
30. A sense amplifier according to claim 21, wherein the sense amplifier circuit comprises:
a third transistor that is connected between a power supply voltage and a first node and that supplies a current to the first node;
a fourth transistor that is connected between the first node and the sense input signal terminal and that supplies a current to the sense input signal terminal line by being turned on in response to the sense amplifier enable signal; and
a second buffer operative to be enabled in response to the sense amplifier enable signal and to buffer a voltage signal of the sense input signal terminal to generate the sense output signal.
31. A sense amplifier according to claim 30, wherein the third and fourth transistors comprise respective PMOS transistors.
32. A sense amplifier according to claim 30, wherein the second buffer generates the sense output signal with a ground voltage when a voltage level of the sense input signal terminal is lower than that of the bias voltage, and generates the sense output signal with a power supply voltage when a voltage level of the sense input signal terminal is higher than that of the bias voltage.