1. A terminal for an electrical armature for connecting a plurality of coil windings to an external connection, said terminal having an arcuate plate like portion formed from an electrically conductive material, at least one terminal tab extending in an axial direction from said plate like portion for receiving an external connecting member, a plurality of coil end winding terminals spaced around the circumference of said plate like portion for connection to coil winding ends, said coil end winding terminals being comprised of a pair of angularly related portions defining a gap to receive a coil winding end and a retaining portion facing said gap and positioned and configured to prevent a coil winding end from moving transversely out of said gap.
2. A terminal for an electrical armature as set forth in claim 1 wherein the winding terminals are formed by bent projections extending radially outwardly from the arcuate plate like portion.
3. A terminal for an electrical armature as set forth in claim 2 wherein the angularly related portions are integrally connected to the arcuate plate like portion and the retaining portion is integrally formed at a side of one of the angularly related portions spaced from the arcuate plate like portion.
4. A terminal for an electrical armature as set forth in claim 3 wherein the retaining portion has a radial edge that has a greater width adjacent a bight of the gap than portions spaced therefrom to facilitate placing a wire end in the gap.
5. A wiring board for an armature having a plurality of axially spaced plate like portions each having one terminal tab and winding terminals as set forth in claim 1 embedded in an insulating material.
6. A wiring board for an electrical armature as set forth in claim 5 wherein the winding terminals are formed by bent projections extending radially outwardly from the arcuate plate like portion.
7. A wiring board for an electrical armature as set forth in claim 6 wherein the angularly related portions are integrally connected to the arcuate plate like portion and the retaining portion is integrally formed at a side of one of the angularly related portions spaced from the arcuate plate like portion.
8. A wiring board for an electrical armature as set forth in claim 7 wherein the retaining portion has a radial edge that has a greater width adjacent a bight of the gap than portions spaced therefrom to facilitate placing a wire end in the gap.
9. A wiring board for an electrical armature as set forth in claim 8 wherein the angularly related portions are bent into engagement and fused to the wire ends.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A fabricating process of a chip package structure, comprising:
providing a first substrate having a plurality of first bonding pads;
providing a second substrate having a plurality of second bonding pads;
forming a plurality of bumps on the first bonding pads of the first substrate;
forming a first two-stage adhesive layer on the first substrate or on the second substrate;
B-stagizing the first two-stage adhesive layer to form a first B-staged adhesive layer;
forming a second two-stage adhesive layer on the first B-staged adhesive layer after the first B-staged adhesive layer is formed;
B-stagizing the second two-stage adhesive layer to form a second B-staged adhesive layer on the first B-staged adhesive layer, wherein a glass transition temperature of the first B-staged adhesive layer is greater than or equal to a glass transition temperature of the second B-staged adhesive layer; and
bonding the first substrate and the second substrate via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.
2. The fabricating process of a chip package structure according to claim 1, wherein the first substrate and the second substrate are both chips.
3. The fabricating process of a chip package structure according to claim 1, wherein the first substrate is a carrier and the second substrate is a chip.
4. The fabricating process of a chip package structure according to claim 1, wherein the first substrate is a chip and the second substrate is a carrier.
5. The fabricating process of a chip package structure according to claim 1, wherein the bumps are stud bumps formed by wire bonder or plating bumps formed by plating process.
6. The fabricating process of a chip package structure according to claim 1, wherein the first two-stage adhesive layer is formed by screen printing, painting, spraying, spin-coating, or dipping.
7. The fabricating process of a chip package structure according to claim 1, wherein the second two-stage adhesive layer is formed by screen printing, painting, spraying, spin-coating, or dipping.
8. The fabricating process of a chip package structure according to claim 1, wherein a method for forming the first B-staged adhesive layer comprises:
forming a plurality of first two-stage adhesive pillars on the first bonding pads or on the second bonding pads; and
B-stagizing the first two-stage adhesive pillars to form a plurality of first B-staged adhesive pillars.
9. The fabricating process of a chip package structure according to claim 8, wherein a method for forming the second B-staged adhesive layer comprises:
forming a plurality of second two-stage adhesive pillars on the first B-staged adhesive pillars; and
B-stagizing the second two-stage adhesive pillars to form a plurality of second B-staged adhesive pillars.
10. The fabricating process of a chip package structure according to claim 9, wherein the first B-staged adhesive pillars are conductive.
11. The fabricating process of a chip package structure according to claim 10, wherein the second B-staged adhesive pillars are conductive.
12. The fabricating process of a chip package structure according to claim 10, wherein the second B-staged adhesive pillars are non-conductive.
13. The fabricating process of a chip package structure according to claim 9, wherein the first B-staged adhesive pillars are non-conductive.
14. The fabricating process of a chip package structure according to claim 13, wherein the second B-staged adhesive pillars are conductive.
15. The fabricating process of a chip package structure according to claim 13, wherein the second B-staged adhesive pillars are non-conductive.
16. The fabricating process of a chip package structure according to claim 1, wherein the first B-staged adhesive layer entirely covers the first substrate and the second B-staged adhesive layer comprises a plurality of second B-staged adhesive pillars.
17. The fabricating process of a chip package structure according to claim 1, wherein a method for B-stagizing the first two-stage adhesive layer and the second two-stage adhesive layer comprises heating or UV curing.
18. A fabricating process of a chip package structure, comprising:
providing a first substrate having a plurality of first bonding pads;
providing a second substrate having a plurality of second bonding pads;
forming a plurality of bumps on the first bonding pads of the first substrate;
forming a first two-stage adhesive layer on the first substrate or on the second substrate;
B-stagizing the first two-stage adhesive layer to form a first B-staged adhesive layer;
forming a second two-stage adhesive layer on the first B-staged adhesive layer after the first B-staged adhesive layer is formed;
B-stagizing the second two-stage adhesive layer to form a second B-staged adhesive layer on the first B-staged adhesive layer, wherein a glass transition temperature of the first B-staged adhesive layer is smaller than a glass transition temperature of the second B-staged adhesive layer; and
bonding the first substrate and the second substrate via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.