1. An electromagnetic relay, comprising:
a fixing contact;
a movable contact configured to be moved to or from the fixing contact in an approaching and separating direction;
a fixed part having a surface, facing the movable contact in the approaching and separating direction, onto which the fixing contact is attached;
a movable part;
a driving part configured to drive the movable part;
a pressing part configured to press the movable contact based on the driving of the movable part; and
a magnetic body having one portion being covered and held and another portion being uncovered, not contacting the fixing contact and directly exposed to an external periphery side of at least one of the fixing contact, the movable contact, and an air space between the fixing contact and the movable contact,
wherein the magnetic body is sandwiched between the fixed part and the movable part.
2. The electromagnetic relay as claimed in claim 1,
wherein the magnetic body includes a fixing side magnetic body positioned at the external periphery side of the fixing contact.
3. The electromagnetic relay as claimed in claim 1,
wherein the magnetic body includes an air space side magnetic body positioned at the external periphery side of the air space.
4. The electromagnetic relay as claimed in claim 1,
wherein the magnetic body overlaps a portion of the surface of the fixed part onto which the fixing contact is attached and a portion of a surface of the movable part onto which the movable contact is attached.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A circuit arrangement, comprising:
first, second and third semiconductor dies physically and electrically coupled to one another in a stack, each semiconductor die including opposing faces, wherein at least one face of each semiconductor die includes circuit logic integrated thereon and defining a circuit layer, and each semiconductor die including an array of conductive through vias extending through such semiconductor die;
a first electricalphysical interconnect physically and electrically coupling the first and second semiconductor dies with one another using a wafer-wafer bonding process; and
a second electricalphysical interconnect physically and electrically coupling the second and third semiconductor dies with one another.
2. The circuit arrangement of claim 1, wherein a first subset of the conductive through vias in each semiconductor die are configured as data-carrying through vias that communicate data between the circuit layer on such semiconductor die and another circuit layer disposed on another semiconductor die in the stack, and wherein a second subset of the conductive through vias are configured as power-carrying through vias that are coupled to a power distribution network for the circuit layer on such semiconductor die.
3. The circuit arrangement of claim 1, wherein the circuit layer in each semiconductor die includes at least one functional unit, wherein at least one face of each semiconductor die includes an inter-layer interface region disposed thereon, wherein each inter-layer interface region on each semiconductor die is disposed at substantially the same topographic location when the respective semiconductor die is disposed within the stack, and wherein the circuit arrangement further comprises an inter-layer bus electrically coupling the functional units on the plurality of semiconductor dies to one another, the inter-layer bus comprising a plurality of electrical conductors disposed within the inter-layer interface region of each semiconductor die and extending between the opposing faces of each semiconductor die, wherein respective electrical conductors disposed in the inter-layer interface regions of adjacent semiconductor dies in the stack are electrically coupled to one another when the plurality of circuit layers are physically and electrically coupled to one another in the stack.
4. The circuit arrangement of claim 1, wherein each semiconductor die includes an array of contact pads disposed on at least one face of such semiconductor die and topographically aligned with the array of conductive through vias, wherein the first electricalphysical interconnect includes a first array of electrical conductors extending between topographically aligned contact pads on the first and second semiconductor dies, and wherein the second electricalphysical interconnect includes a second array of electrical conductors extending between topographically aligned contact pads on the second and third semiconductor dies.
5. The circuit arrangement of claim 4, wherein the plurality of electrical conductors in each of the first and second electricalphysical interconnects comprise a plurality of micro C? interconnects.
6. The circuit arrangement of claim 4, wherein the array of contact pads disposed on each semiconductor die is a regular array, wherein a first subset of the contact pads in the array of contact pads on each semiconductor die are configured as data-carrying contact pads that are electrically coupled to data-carrying through vias, wherein a second subset of the contact pads in the array of contact pads on each semiconductor die are configured as power-carrying contact pads that are electrically coupled to power-carrying through vias, and wherein a third subset of the contact pads are dummy contact pads that are not topographically aligned with any of the conductive through vias.
7. The circuit arrangement of claim 4, wherein the first electricalphysical interconnect has a higher interconnect density than the second electricalphysical interconnect.
8. The circuit arrangement of claim 1, wherein the first electricalphysical interconnect is formed while the first and second semiconductor dies are disposed on first and second semiconductor wafers, and wherein the first and second semiconductor dies are separated from the first and second wafers after the first electricalphysical interconnect is formed.
9. The circuit arrangement of claim 8, wherein the first and second semiconductor dies are separated from the first and second semiconductor wafers before the second electricalphysical interconnect is formed, and wherein the second electricalphysical interconnect is formed using a chip-chip bonding process.
10. The circuit arrangement of claim 8, wherein the first and second semiconductor dies are separated from the first and second semiconductor wafers after the second electricalphysical interconnect is formed, and wherein the second electricalphysical interconnect is formed using a chip-wafer bonding process.
11. The circuit arrangement of claim 8, wherein the first and second semiconductor dies each include an array of through silicon vias (TSVs) formed therein by partially etching a regular array of holes in the first and second semiconductor wafers from the first surface thereof, thinning the first and second semiconductor wafers to expose the regular array of holes on a second surface of the first and second semiconductor wafers, and forming the TSVs in the regular array of holes in the first and second semiconductor wafers.
12. The circuit arrangement of claim 1, wherein the first and third semiconductor dies differ from one another by at least one of size, thickness and aspect ratio.
13. A program product, comprising at least one hardware design file defining the plurality of circuit layers of claim 1, and a non-transitory computer readable storage medium storing the at least one hardware design file.