1. A filter element comprising:
a filter member provided with a plurality of pleat portions; and
a frame body holding an outer peripheral portion of the filter member,
wherein the frame body is provided with a comb-shaped member having a comb-tooth portion which is inserted into adjacent pleat portions and contacts to a surface of the filter member, and the comb-shaped member is formed by an insert-molding process,
wherein a projection is formed to at least one end of the comb-shaped member so as to extend in a longitudinal direction thereof, and
wherein the projection is firmly embedded into the frame body, and
wherein holding portions are formed to both the ends of the comb-shaped member at which the holding portions continuously contact so as to surround the outer peripheral edges of the ends of the comb-shaped member.
2. The filter element according to claim 1, wherein the comb-shaped member is disposed in a clean side of the filter member.
3. The filter element according to claim 1, wherein the frame body is formed with holding portions which hold outer peripheral edges of both ends of the comb-shaped member in the longitudinal direction thereof.
4. The filter element according to claim 1, wherein the comb-tooth portion has a tip end formed in circular-arc shape.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising a driver circuit, the driver circuit comprising:
n cells arranged in a first direction, each of n cells having an input terminal and an output terminal, n being an integer greater than or equal to 2;
n input signal lines, each corresponding to one of the n cells and connected to the input terminal of the corresponding cell; and
n output signal lines, each corresponding to one of the n cells and connected to the output terminal of the corresponding cell,
wherein the n input signal lines and the n output signal lines extend in the first direction, and
wherein the total number of input signal lines and output signal lines which are provided over one of the n cells is (n\u22121).
2. The semiconductor device according to claim 1, wherein the total number of intersections of a straight line connecting the input terminal and the output terminal, and the input signal lines or the output signal lines provided over each of the n cells is (n\u22121) in one of the n cells.
3. The semiconductor device according to claim 1, wherein the n input signal lines and the n output signal lines are provided over an insulating layer provided between the n cells, and the n input signal lines and the n output signal lines.
4. A semiconductor device comprising a driver circuit, the driver circuit comprising:
n cells arranged in a first direction, each of n cells having an input terminal and an output terminal, n being an integer greater than or equal to 2;
n input signal lines, each corresponding to one of the n cells and connected to the input terminal of the corresponding cell; and
n output signal lines, each corresponding to one of the n cells and connected to the output terminal of the corresponding cell,
wherein the n input signal lines and the n output signal lines extend in the first direction,
wherein each of the (n\u22121) input signal lines other than a first input signal line includes at least one bending region,
wherein each of the (n\u22121) output signal lines other than n-th output signal line includes at least one bending region, and
wherein the total number of input signal lines and output signal lines which are provided over one of the n cells is (n\u22121).
5. The semiconductor device according to claim 4, wherein the total number of intersections of a straight line connecting the input terminal and the output terminal, and the input signal lines or the output signal lines provided over each of the n cells is (n\u22121) in one of the n cells.
6. The semiconductor device according to claim 4, wherein the n input signal lines and the n output signal lines are provided over an insulating layer provided between the n cells, and the n input signal lines and the n output signal lines.
7. A semiconductor device comprising:
a memory cell array including a plurality of memory cells; and
a driver circuit arranged in the periphery of the memory cell array,
wherein the driver circuit comprises:
n cells arranged in a first direction, each of n cells having an input terminal and an output terminal, n being an integer greater than or equal to 2;
n input signal lines, each corresponding to one of the n cells and connected to the input terminal of the corresponding cell; and
n output signal lines, each corresponding to one of the n cells and connected to the output terminal of the corresponding cell,
wherein the n input signal lines and the n output signal lines extend in the first direction,
wherein the total number of input signal lines and output signal lines which are provided over one of the n cells is (n\u22121), and
wherein input terminals included in the memory cell array and then output signal lines are electrically connected to one another.
8. The semiconductor device according to claim 7, wherein the total number of intersections of a straight line connecting the input terminal and the output terminal, and the input signal lines or the output signal lines provided over each of the n cells is (n\u22121) in one of the n cells.
9. The semiconductor device according to claim 7, wherein the n input signal lines and the n output signal lines are provided over an insulating layer provided between the n cells, and the n input signal lines and the n output signal lines.
10. The semiconductor device according to claim 7, wherein the first direction is a row direction of the memory cell array.
11. The semiconductor device according to claim 7, wherein the first direction is a column direction of the memory cell array.
12. The semiconductor device according to claim 7, wherein each of the memory cells comprises a first transistor, a second transistor, and a capacitor.
13. The semiconductor device according to claim 12, wherein the first transistor comprises an oxide semiconductor.
14. A semiconductor device comprising:
a memory cell array including a plurality of memory cells; and
a driver circuit arranged in the periphery of the memory cell array,
wherein the driver circuit comprises:
n cells arranged in a first direction, each of n cells having an input terminal and an output terminal, n being an integer greater than or equal to 2;
n input signal lines, each corresponding to one of the n cells and connected to the input terminal of the corresponding cell; and
n output signal lines, each corresponding to one of the n cells and connected to the output terminal of the corresponding cell,
wherein the n input signal lines and the n output signal lines extend in the first direction,
wherein each of the (n\u22121) input signal lines other than a first input signal line includes at least one bending region,
wherein each of the (n\u22121) output signal lines other than n-th output signal line includes at least one bending region,
wherein the total number of input signal lines and output signal lines which are provided over one of the n cells is (n\u22121), and
wherein input terminals included in the memory cell array and the n output signal lines are electrically connected to one another.
15. The semiconductor device according to claim 14, wherein the total number of intersections of a straight line connecting the input terminal and the output terminal, and the input signal lines or the output signal lines provided over each of the n cells is (n\u22121) in one of the n cells.
16. The semiconductor device according to claim 14, wherein the n input signal lines and the n output signal lines are provided over an insulating layer provided between the n cells, and the n input signal lines and the n output signal lines.
17. The semiconductor device according to claim 14, wherein the first direction is a row direction of the memory cell array.
18. The semiconductor device according to claim 14, wherein the first direction is a column direction of the memory cell array.
19. The semiconductor device according to claim 14, wherein each of the memory cells comprises a first transistor, a second transistor, and a capacitor.
20. The semiconductor device according to claim 19, wherein the first transistor comprises an oxide semiconductor.