1. An integrated circuit, comprising:
an array of non-volatile memory cells, each memory cell of the array having a charge storage region and a plurality of terminals; and
a discharge rate control circuit for controlling a discharge rate of one or more of the plurality of terminals of an erased memory cell, the discharge rate control circuit comprising:
a reference current generator for providing a reference current; and
a first current mirror, coupled to the reference current generator, for providing a first predetermined discharge current for discharging a first predetermined terminal of the plurality of terminals after the erase operation.
2. The integrated circuit of claim 1, wherein the discharge rate control circuit is for discharging all of the plurality of terminals at a rate determined to reduce voltage overshoot due to capacitive coupling between one or more of the plurality of terminals.
3. The integrated circuit of claim 2, wherein the plurality of terminals comprises a control gate, a drain, and a source.
4. The integrated circuit of claim 1, wherein the first and second predetermined terminals are both discharged at a first rate for a first predetermined time period and discharged at a second rate for a second predetermined time period, wherein the second rate is higher than the first rate.
5. The integrated circuit of claim 1, wherein the first predetermined terminal of the plurality of terminals is discharged at a first rate for a first predetermined time period and discharged at a second rate for a second predetermined time period, wherein the second rate is higher than the first rate.
6. The integrated circuit of claim 1, further comprising a second current mirror, coupled to the reference current generator, for providing a second predetermined discharge current for discharging a second predetermined terminal of the plurality of terminals after the erase operation.
7. The integrated circuit of claim 6, wherein the second current mirror comprises:
a first transistor having a first current electrode and a control electrode both coupled to the reference current generator, and a second current electrode coupled to a first supply voltage terminal;
a second transistor having a first current electrode capable of being selectively coupled to the well terminal of each of the array of memory cells, a control electrode coupled to the reference current generator, and a second current electrode coupled to the first supply voltage terminal.
8. The integrated circuit of claim 1, wherein the first current mirror comprises:
a third transistor having a first current electrode and a control electrode both coupled to the reference current generator, and a second current electrode selectively coupled to the source and drain of each memory cell of the array of memory cells; and
a fourth transistor having a having a first current electrode coupled to a source of each memory cell of the array of memory cells, a control electrode coupled to the reference current generator, and a second current electrode selectively coupled to the control gate of each memory cell of the array of memory cells.
9. The integrated circuit of claim 1, further comprising a third current mirror, the third current mirror having an input for receiving the second predetermined discharge current, the third current mirror providing a discharge path from predetermined terminals of each memory cell of the array, for recycling charge from the predetermined terminals to a supply voltage terminal.
10. The integrated circuit of claim 1, wherein the discharge rate control circuit further comprises a second reference current generator coupled to the first and second current mirrors.
11. The integrated circuit of claim 1, wherein the drain of each of the memory cells of the array is coupled to a corresponding bit line and all of the sources of the array are coupled together.
12. The integrated circuit of claim 1, wherein the charge storage region is a floating gate of a flash memory cell.
13. An integrated circuit, comprising:
an array of non-volatile memory cells, each memory cell of the array having a control gate, a source, a drain, and a well terminal;
a reference current generator for providing a reference current;
a first current mirror, coupled to the reference current generator, for providing a first predetermined discharge current for discharging the control gate of each memory cell of the array of non-volatile memory cells after an erase operation of the array; and
a second current mirror, coupled to the reference current generator, for providing a second predetermined discharge current for discharging the well terminal of each memory cell of the array of non-volatile memory cells after the erase operation of the array.
14. The integrated circuit of claim 13, wherein the array is erased by applying a positive voltage to the well terminal of each memory cell while applying a negative voltage to the control gate of each memory cell.
15. The integrated circuit of claim 13, wherein the array comprises a plurality of flash memory cells.
16. The integrated circuit of claim 13, wherein the control gate, the drain, the source and the well terminal are all discharged at a rate whereby a discharge voltage overshoot, caused by capacitive coupling between one or more memory cell terminals, is minimized.
17. The integrated circuit of claim 13, wherein the control gate is discharged at a first rate for a first predetermined time period and discharged at a second rate for a second predetermined time period, wherein the second rate is higher than the first rate.
18. The integrated circuit of claim 13, wherein the control gate and the well terminal are both discharged at a first rate for a first predetermined time period and discharged at a second rate for a second predetermined time period, wherein the second rate is higher than the first rate.
19. The integrated circuit of claim 13, wherein each of the memory cells further comprises a deep well terminal coupled to the second current mirror, wherein the deep well terminal is discharged by second discharge current after the erase operation.
20. An integrated circuit comprising:
an array of non-volatile memory cells, each memory cell of the array having a control gate, a source, a drain, a first well terminal, and a second well terminal; and
a discharge rate control circuit for controlling discharging of erase voltages from the control gate, the source, the drain, the first well terminal and the second well terminal of an erased memory cell after an erase operation of the array of non-volatile memory cells.
21. The integrated circuit of claim 20, wherein the discharge rate control circuit comprises:
a reference current generator for providing a reference current; and
a plurality of current mirrors for providing a plurality of discharge currents in response to the reference current, the plurality of current mirrors for discharging the erase voltages at a plurality of predetermined rates.
22. The integrated circuit of claim 20, wherein a discharge rate of the erase voltages is determined to reduce voltage overshoot due to capacitive coupling between one or more of the control gate, the source, the drain, the first well terminal and the second well terminal.
23. The integrated circuit of claim 20, wherein the array of non-volatile memory cells comprises an array of flash memory cells.
24. The integrated circuit of claim 20, wherein the control gate is discharged at a first rate for a first predetermined time period and discharged at a second rate for a second predetermined time period, wherein the second rate is higher than the first rate.
25. The integrated circuit of claim 20, wherein the control gate and the first well terminal are both discharged at a first rate for a first predetermined time period and discharged at a second rate for a second predetermined time period, wherein the second rate is higher than the first rate.
26. A method for controlling a discharge rate of an erase voltage applied to a non-volatile memory cell, the non-volatile memory cell having a plurality of terminals, the method comprising:
providing a reference current;
mirroring the reference current to provide a first mirrored current for discharging a first terminal of the plurality of terminals at a first discharge rate for a first predetermined time; and
mirroring the reference current to provide a second mirrored current for discharging a second terminal of the plurality of terminals at a second discharge rate for a second predetermined time.
27. The method of claim 26, wherein the plurality of terminals comprises a control gate, a floating gate, a source, a drain, and a well region, the well region being in a semiconductor substrate.
28. The method of claim 26, wherein the first discharge rate is approximately equal to the second discharge rate and the first predetermined time is approximately equal to the second predetermined time.
29. The method of claim 26, further comprising:
discharging the first terminal at a third discharge rate for a third predetermined time; and
discharging the second terminal at a fourth discharge rate for a fourth predetermined time.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A vehicle seat assembly comprising:
a pair of right and left seat slide rails including:
a pair of right and left lower rails each fixed onto a floor portion of an occupant compartment to extend in a longitudinal direction of a vehicle body, and
a pair of right and left upper rails slidably supported along corresponding ones of said lower rails; and
a pair of right and left seat-cushion frames each supported by a corresponding one of said seat slide rails in such a manner as to be moved in said longitudinal direction together with a corresponding one of said upper rails,
a coupling member coupling a front end of each of said seat-cushion frames to a corresponding one of said upper rails;
a rear link member provided in a rear end of each of said seat-cushion frames; and
a vehicle body-side support member provided on the side of the vehicle body to support said rear link member,
wherein:
said rear link member including:
a pivoted portion pivotally supported by said upper rail,
a coupled portion coupled to the rear end of said seat-cushion frame, and
an engaged portion engaged with said vehicle body-side support member; and
said vehicle body-side support member including:
a sliding drive portion which slidably supports said engaged portion of said rear link member to allow said rear link member to be swingingly displaced about said pivoted portion in conjunction with a longitudinal movement of said seat-cushion frame, so as to move said coupled portion of said rear link member in an upwarddownward direction to drivingly lift and lower the rear end of said seat-cushion frame.
2. The vehicle seat assembly as defined in claim 1, wherein:
said pivoted portion associated with said upper rail is provided in a front region of said rear link member;
said coupled portion associated with said seat-cushion frame is provided in a rear upper region of said rear link member; and
said engaged portion associated with said vehicle body-side support member is provided in a lower region of said rear link member.
3. The vehicle seat assembly as defined in claim 2, wherein said rear link member is formed in an approximately triangular shape in side view, wherein said pivoted portion, said coupled portion and said engaged portion are provided in three apex regions of said rear link member, respectively.
4. The vehicle seat assembly as defined in claim 3, wherein a positional relationship of said pivoted portion, said coupled portion and said engaged portion provided in said rear link member is set such that, when said rear link member is moved to a lift position for drivingly lifting said seat-cushion frame, said coupled portion associated with said seat-cushion frame is displaced to be located in an uppermost apex region of said rear link member formed in an approximately triangular shape in side view.
5. The vehicle seat assembly as defined in claim 2, wherein said vehicle body-side support member is formed with a gentle S-shaped sliding groove having, in side view, an upward inclination which gently increases and then gently decreases in a direction from a rear end to a front end of said vehicle seat assembly, wherein said engaged portion of said rear link member is slidably engaged with said sliding groove.
6. The vehicle seat assembly as defined in claim 2, wherein said vehicle body-side support member is formed with a sliding groove having, in side view, an inclination which linearly increases in a direction from a rear end to a front end of said vehicle seat assembly, wherein said engaged portion of said rear link member is slidably engaged with said sliding groove.
7. The vehicle seat assembly as defined in claim 1, further comprising a connection member connecting between the respective rear ends of said pair of right and left seat-cushion frames, wherein said coupled portion of said rear link member is coupled to said connection member.
8. The vehicle seat assembly as defined in claim 1, further comprising:
a seat-cushion support member disposed in a front end of each of said seat-cushion frames to support a seat cushion;
a pivot member pivotally mounting said seat-cushion support member to said seat-cushion frame; and
an angle adjustment mechanism adapted to swingingly displace said seat-cushion support member about said pivot member so as to adjust an angular position of said seat cushion.
9. The vehicle seat assembly as defined in claim 8, wherein:
said pivot member associated with said seat-cushion frame is provided in a rear end of said seat-cushion support member; and
said angle adjustment mechanism is disposed frontwardly relative to said pivot member.
10. The vehicle seat assembly as defined in claim 9, further comprising a motion-transmitting mechanism, wherein said angle adjustment mechanism is associated with one of said seat-cushion support members disposed on right and left sides of said seat cushion, wherein said motion-transmitting mechanism transmits a motion input to said one of said seat-cushion support members from said angle adjustment mechanism, to the other one of said seat-cushion support members so as to swingingly displace said other one of seat-cushion support members.
11. The vehicle seat assembly as defined in claim 10, wherein said motion-transmitting mechanism includes: a pair of right and left front link members each having a base end pivotally supported by a corresponding one of said seat-cushion frames and a distal end coupled to a corresponding one of said seat-cushion support members; and an interlock member interlockingly connecting between the respective base ends of said front link members, said motion-transmitting mechanism being operable to transmit a motion input to said one of said seat-cushion support members and one of said front link members from said angle adjustment mechanism, to the other one of said front link members and said the other one of seat-cushion support members through said interlock member so as to swingingly displace said the other one of seat-cushion support members simultaneously with said one of said seat-cushion support members.
12. The vehicle seat assembly as defined in claim 1, wherein:
said rear link member is formed as an arm-shaped member which has a central region provided with said pivoted portion associated with said upper rail, and opposite ends provided, respectively, with said coupled portion associated with said seat-cushion frame and said engaged portion associated with said vehicle body-side support member; and
said vehicle body-side support member includes an extension portion extending downwardly from a longitudinally central region of a corresponding one of said lower rails, in side view,
wherein said sliding drive portion is provided in said extension portion with a frontwardly-downward inclination.
13. The vehicle seat assembly as defined in claim 1, wherein said vehicle body-side support member including said sliding drive portion is disposed on a laterally inward side relative to each of said seat slide rails.