1. A method for fabricating a flash memory, comprising:
providing a semiconductor substrate
forming a first dielectric layer on a surface of the semiconductor substrate;
forming a first semiconductor layer on a surface of the first dielectric layer;
performing an ion implantation process onto a portion of the first semiconductor layer corresponding to a position of a subsequently formed floating gate;
performing an oxygen ion implantation process onto a portion of the first semiconductor layer between the position of the subsequently formed floating gate and the position of a subsequently formed first select gate to form an oxide layer;
forming a second dielectric layer having an opening exposing the position of the first select gate on the first semiconductor layer;
forming a second semiconductor layer on the second dielectric layer; and
forming a flash cell and a select gate structure by etching the first dielectric layer, the first semiconductor layer, the oxide layer, the second dielectric layer and the second semiconductor layer.
2. The method according claim 1, wherein:
the flash cell includes the N-type doped portion of the first semiconductor layer as the floating gate and a portion of the second semiconductor layer as a control gate; and
the select gate structure includes the first select gate formed by the portion of the first semiconductor exposed by the opening as the first select gate and a portion of the second semiconductor layer as a second select gate.
3. The method according claim 1, wherein:
ions for the ion implantation process are N-type ions.
4. The method according claim 1, before performing the ion implantation process onto the portion of the first semiconductor layer corresponding to the position of a subsequently formed floating gate, further including:
forming a first mask layer having a first opening exposing the portion of the first semiconductor layer corresponding to the position of the floating gate on the surface of the first semiconductor layer.
5. The method according claim 2, before performing the oxygen ion implantation process onto the portion of the first semiconductor layer between the position of the subsequently formed floating gate and the position of the subsequently formed first select gate, further including:
removing the first mask layer; and
forming a second mask layer having a second opening exposing the portion of the semiconductor layer between the position of the subsequently formed floating gate and the position of the subsequently formed first select gate.
6. The method according to claim 1, after performing the oxygen ion implantation process onto a portion of the first semiconductor layer between the position of the subsequently formed floating gate and the position of the subsequently formed first select gate, further including:
performing a first thermal annealing process.
7. The method according claim 1, after forming the second dielectric layer having an opening exposing the position of the first select gate, further including:
forming a third mask layer having a third opening exposing the position of the first select gate; and
forming the opening exposing the position of the first select gate by etching the second dielectric layer using the third mask layer as a mask.
8. The method according claim 1, wherein:
the first semiconductor layer is made of poly silicon; and
the second semiconductor layer is made of poly silicon.
9. The method according to claim 1, after forming the flash cell and the select gate structure, further including:
forming sidewall spacers on side surfaces of the flash cell and the select gate structure.
10. The method according to claim 1, after forming the second semiconductor layer, further including:
performing a P-type ion implantation process onto the second semiconductor layer; and
performing a second thermal annealing process.
11. The method according to claim 1, wherein:
N-type ions of the N-type ion implantation process include phosphorous ions, or arsenic ions.
12. The method according to claim 1, wherein:
a dose of the oxygen ion implantation process is in a range of approximately 5E12 atomcm2\u02dc1E15 atomcm2;
an energy of the oxygen ion implantation process is in a range of approximately 1 KeV\u02dc50 KeV; and
an implantation angle of the oxygen ion implantation process is in a range of approximately \u22125\xb0\u02dc5\xb0.
13. The method according to claim 1, wherein:
a thickness of the first semiconductor layer is in a range of approximately 500 \u212b\u02dc2000 \u212b.
14. The method according to claim 1, wherein:
a width of the oxide layer is equal to, or smaller than a minimum distance between the floating gate and the first select gate
15. The method according to claim 8, wherein:
a dose of the P-type ion implantation is in a range of approximately 5E14 atomcm2\u02dc5E15 atomcm2.
16. A flash memory, comprising:
a semiconductor substrate;
a flash cell having a floating gate dielectric layer formed on a surface of the semiconductor substrate, a floating gate formed on the floating gate dielectric layer, a control gate dielectric layer formed on the floating gate and the a control gate formed on the control gate dielectric layer formed on the semiconductor substrate;
a select gate structure having a select gate dielectric layer formed on the surface of the semiconductor substrate, a first select gate formed on the select gate dielectric layer and a second select gate formed on the first select gate formed on the semiconductor substrate;
a co-sourcedrain region formed in the semiconductor substrate between the flash cell and the select gate structure;
a source region in the semiconductor substrate at the other side of the flash cell; and
a drain region in the semiconductor substrate at the other side of the select gate structure.
17. The flash memory according to claim 16, wherein the flash cell and the select gate structure are formed by:
forming a first dielectric layer on a surface of the semiconductor substrate;
forming a first semiconductor layer on a surface of the first dielectric layer;
performing an ion implantation process onto a portion of the first semiconductor layer corresponding to a position of a subsequently formed floating gate;
performing an oxygen ion implantation process onto a portion of the first semiconductor layer between the position of the subsequently formed floating gate and a position of a subsequently formed first select gate to form an oxide layer;
forming a second dielectric layer having an opening exposing the position of the first select gate on the first semiconductor layer;
forming a second semiconductor layer on the second dielectric layer; and
forming a flash cell and a select gate structure by etching the first dielectric layer, the first semiconductor layer, the oxide layer, the second dielectric layer and the second semiconductor layer.
18. The flash memory according to claim 16, wherein:
the second dielectric layer includes a silicon oxide layer, a silicon nitride layer formed on the silicon oxide layer and a silicon oxide layer formed on the silicon nitride layer.
19. The flash memory according to claim 16, wherein:
the first semiconductor layer is made of poly silicon; and
the second semiconductor layer is made of poly silicon.
20. The flash memory according to claim 16, wherein:
sidewall spacers are formed on side surfaces of the flash cell and the select gate structure.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method in a mobile communication system for transferring information in a fixed-length message from a base station to at least one mobile station, wherein
content information is transferred in the payload portion of the message for defining the contents of the payload portion of the message, and
information elements defined by said content information are transferred in the payload portion of the message according to said content information.
2. A method according to claim 1 wherein said information elements comprise at least information elements containing position data.
3. A method according to claim 2 wherein said information elements define the location of at least one neighbor base station relative to the base station.
4. A method according to claim 1 wherein said content information defines a value range for data to be transferred corresponding to the binary value range of at least one information element.
5. A method according to claim 1 wherein said content information defines the magnitude of the step of the value of data to be transferred corresponding to the smallest binary value step of at least one information element.
6. A method according to claim 1 wherein information elements of predetermined length are transferred in the payload portion of the message in addition to the information elements defined in said content information.
7. A method according to claim 1 wherein said fixed-length message is an SMS-CB message.