1. A high refractive index, high dispersion optical glass for precision molding, having a yield temperature (At) of at most 550\xb0 C., refractive index (nd) of at least 1.83 and Abbe number (\u03bdd) of at most 26.0, which is represented, in term of atoms for making up the glass, by the following chemical composition (wt %):
P2O5
15 to 29%
B2O3
\u20020 to 2%
GeO2
\u20020 to 14%
Sum of P2O5 + B2O3 + GeO2
20 to 35%
Li2O
\u20020 to 5%
Na2O
\u20023 to 14%
K2O
\u20020 to 9%
Sum of Li2O + Na2O + K2O
\u20025 to 15%
Nb2O5
\u20022 to less than 22%
Bi2O3
34 to 60%
WO3
\u20020 to 5%
BaO
\u20020 to 5%
In2O3
\u20020 to 7%
2. A high refractive index, high dispersion optical glass for precision molding, having a yield temperature (At) of at most 550\xb0 C., refractive index (nd) of at least 1.83 and Abbe number (\u03bdd) of at most 26.0, which is represented, in term of atoms for making up the glass, by the following chemical composition (wt %):
P2O5
\u200916 to 28%
B2O3
\u2002\u20090 to 1%
GeO2
\u2002\u20090 to 13.5%
Sum of P2O5 + B2O3 + GeO2
\u200922 to 33%
Li2O
\u2002\u20090 to 3%
Na2O
\u2002\u20094 to 13%
K2O
\u2002\u20090 to 8%
Sum of Li2O + Na2O + K2O
\u2002\u20097 to 13%
Nb2O5
2.5 to 21.5%
Bi2O3
\u200936 to 59%
WO3
\u2002\u20090 to 3%
BaO
\u2002\u20090 to 3%
In2O3
\u2002\u20090 to 5%
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for fabricating a ferroelectric device, comprising the steps of:
forming an interlayer insulating layer on a semiconductor substrate, the interlayer insulating layer having a buried contact plug;
forming an oxidation barrier layer on the interlayer insulating layer and on the contact plug in order to prevent oxidation of the contact plug;
forming a ferroelectric capacitor on the oxidation barrier layer and on the contact plug;
forming a diffusion barrier layer pattern to completely cover the ferroelectric capacitor;
etching a portion of the oxidation barrier layer that is exposed by the diffusion barrier layer pattern.
2. The method according to claim 1, wherein forming the oxidation barrier layer is preceded by forming an adhesion layer on the interlayer insulating layer, wherein etching the exposed portion of the oxidation barrier layer comprises:
depositing a diffusion barrier layer on the ferroelectric capacitor and over the oxidation barrier layer;
using a photoresist mask and patterning the diffusion barrier layer to form the diffusion barrier layer pattern; and
using the pattern of the diffusion barrier layer as a mask and etching the oxidation barrier layer and the adhesion layer to form a pattern of the oxidation barrier layer and a pattern of the adhesion layer until the interlayer insulating layer is exposed, wherein the diffusion barrier layer prevents materials from diffusing into andor out of the ferroelectric capacitor.
3. The method according to claim 2, wherein the pattern of the oxidation barrier layer and the pattern of the adhesion layer extend outwardly from lateral surfaces of the ferroelectric capacitor.
4. The method according to claim 2, further comprising annealing the diffusion barrier layer in an ambient oxygen atmosphere at a temperature of about 650 degrees C. for about 30 minutes.
5. The method according to claim 1, wherein forming the interlayer insulating layer comprises:
forming a transistor on the semiconductor substrate;
forming a first interlayer insulating layer over the semiconductor substrate and the transistor;
forming a first metal line, which is electrically connected to the substrate through the first interlayer insulating layer, on the first interlayer insulating layer; and
depositing a second interlayer insulating layer.
6. The method according to claim 5, further comprising:
depositing a third interlayer insulating layer over the second interlayer insulating layer and the ferroelectric capacitor;
forming a second metal line on the third interlayer insulating layer;
depositing a fourth interlayer insulating layer over the third interlayer insulating layer and the second metal line; and
forming a third metal line on the fourth interlayer insulating layer to be electrically connected to an upper electrode of the ferroelectric capacitor.
7. The method according to claim 6, further comprising:
forming the first metal line from tungsten (W);
forming the second metal line from a stacked layer of titanium (Ti), titanium nitride (TiN), aluminum (Al) and titanium nitride (TiN) layer; and
forming the third metal line from aluminum (Al).
8. The method according to claim 1, further comprising:
forming the oxidation barrier layer from a material selected from the group consisting of iridium (Ir), rhodium (Rh) and ruthenium (Ru); and
forming the adhesion layer from titanium (Ti).
9. The method according to claim 1, wherein forming the ferroelectric capacitor comprises:
forming a lower electrode layer on the oxidation barrier layer;
forming a ferroelectric film on the lower electrode layer;
forming an upper electrode layer on the ferroelectric layer;
performing photolithography and etching the upper electrode layer; and
performing a second photolithography and etching the ferroelectric film and the lower electrode layer until the oxidation barrier layer is exposed.
10. The method according to claim 1, wherein forming the ferroelectric capacitor comprises:
forming a lower electrode layer on the oxidation barrier layer;
forming a ferroelectric film on the lower electrode layer;
forming an upper electrode layer on the ferroelectric layer, and
performing photolithography and sequentially etching the upper electrode layer, ferroelectric layer and lower electrode layer until the oxidation barrier layer is exposed.
11. The method according to claim 9, further comprising:
forming the lower electrode layer from a double layer of iridium dioxide (IrO2) and platinum (Pt); and
forming the upper electrode layer from a double layer of iridium dioxide (IrO2) and iridium (Ir).
12. The method according to claim 10, further comprising:
forming the lower electrode layer from a double layer of iridium dioxide (IrO2) and platinum (Pt); and
forming the upper electrode layer from a double layer of iridium dioxide (IrO2) and iridium (Ir).
13. The method according to claim 9, further comprising forming the lower electrode layer and upper electrode from the same material selected from a group consisting of either platinum (Pt), iridium (Ir), ruthenium (Ru), a combination of a conductive oxide thereof, and a double layer of iridium dioxide (IrO2) and platinum (Pt).
14. The method according to claim 10, further comprising forming the lower electrode layer and upper electrode from the same material selected from a group consisting of either platinum (Pt), iridium (Ir), ruthenium (Ru), a combination of a conductive oxide thereof, and a double layer of iridium dioxide (IrO2) and platinum (Pt).
15. A method for fabricating a one transistor and one capacitor ferroelectric memory device, comprising the steps of:
forming a transistor comprising a gate electrode and sourcedrain regions on a semiconductor substrate;
forming a first interlayer insulating layer over the semiconductor substrate and the transistor;
forming a first metal line, which is electrically connected to one of the sourcedrain regions, on the first interlayer insulating layer;
forming a second interlayer insulating layer over the first interlayer insulating layer and the first metal line;
forming a contact plug electrically connected to the other of the sourcedrain regions through the second and first interlayer insulating layers;
forming an adhesion layer on the second interlayer insulating layer and on the contact plug;
forming an oxidation barrier layer on the adhesion layer;
forming a ferroelectric capacitor on the adhesion layer;
forming a diffusion barrier layer pattern to completely cover the ferroelectric capacitor on the oxidation barrier layer;
using the diffusion barrier layer pattern as a mask and etching the oxidation barrier layer and adhesion layer to form an oxidation barrier layer pattern and an adhesion layer pattern;
forming a third interlayer insulating layer over the second interlayer insulating layer and the adhesion layer pattern;
forming a second metal line, which is electrically connected to the gate electrode of the transistor, on the third interlayer insulating layer;
forming a fourth interlayer insulating layer over the third interlayer insulating layer and the second metal line; and
forming a third metal line, which is electrically connected to the ferroelectric capacitor, on the fourth interlayer insulating layer.
16. The method according to claim 15, wherein forming the ferroelectric capacitor comprises:
sequentially depositing a lower electrode layer, a ferroelectric film and an upper electrode layer on the oxidation barrier layer; and
patterning the upper electrode layer, ferroelectric film, and lower electrode layer.
17. The method according to claim 16, wherein patterning the upper electrode layer, ferroelectric film, and lower electrode layer comprises:
etching the upper electrode layer to form an upper electrode pattern; and
sequentially etching the ferroelectric film and the lower electrode layer down to a top surface of the oxidation barrier layer to form a ferroelectric electric film pattern and a lower electrode pattern, respectively.
18. The method according to claim 15, wherein forming the diffusion barrier layer pattern to completely cover the ferroelectric capacitor on the oxidation barrier layer comprises:
forming a diffusion barrier layer to completely cover the ferroelectric capacitor on the oxidation barrier layer; and
patterning the diffusion barrier layer to form the diffusion barrier layer pattern extending outwardly from the lateral surface of the ferroelectric capacitor.
19. The method according to claim 15, further comprising:
forming the first metal line from tungsten (W);
forming the second metal line from a stacked layer of titanium (Ti), titanium nitride (TiN), aluminum (Al) and titanium nitride (TiN) layer; and
forming the third metal line from aluminum (Al).
20. The method according to claim 15, further comprising:
forming the oxidation barrier layer from a material selected from the group consisting of iridium (Ir), iridium dioxide (IrO2), ruthenium (Ru) or rhodium (Rh);
forming an adhesion layer from titanium (Ti); and
forming the diffusion barrier layer from a material selected from the group consisting of titanium dioxide (TiO2) and alumina (Al2O3).
21. The method according to claim 1, further comprising, before etching the portion of the oxidation barrier layer, annealing the diffusion barrier layer pattern.
22. The method according to claim 17, further comprising, before etching the exposed oxidation barrier layer, annealing the diffusion barrier layer.