What is claimed is:
1. A semiconductor device, comprising:
a first node which is provided a first voltage;
a second node which is provided a second voltage, wherein said second voltage is lower than said first voltage;
a first current mirror circuit which has an input terminal and an output terminal, wherein said first current mirror circuit is coupled with said first node;
a second current mirror circuit which has an input terminal and an output terminal, wherein said input terminal of said second current mirror circuit is coupled with said output terminal of said first current mirror circuit, wherein said output terminal of said second current mirror circuit is coupled with said input terminal of said first current mirror circuit and wherein said second current mirror circuit is coupled with said second node;
a start-up circuit which supplies current to said input terminal of said second current mirror circuit based on voltage on said input terminal of said first current mirror circuit.
2. The semiconductor device in accordance with claim 1, wherein said start-up circuit comprises;
a third node;
a capacitance element which is coupled between said third node and said second node;
a first switch which has an ON state and an OFF state, and which is coupled between said first node and said input terminal of said second current mirror circuit; and
a second switch which has an ON state and an OFF state, and which is coupled between said first node and said third node.
3. The semiconductor device in accordance with claim 2, wherein said first switch comprises a first transistor which has a control electrode coupling with said third node, a first electrode coupling with said first node and a second electrode coupling with said input terminal of said second current mirror circuit, and wherein said second switch comprises a second transistor which has a control electrode coupling with said input terminal of said first current mirror circuit, a first electrode coupling with said first node and a second electrode coupling with said third node.
4. The semiconductor device in accordance with claim 3, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said input terminal thereof, and a fourth transistor which has a first electrode coupling with said first node, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said output terminal thereof; and wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said input terminal thereof, and a sixth transistor which has a first electrode coupling with said second node through a resistor, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said output terminal thereof.
5. The semiconductor device in accordance with claim 3, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said input terminal thereof, and a fourth transistor which has a first electrode coupling with said first node through a resistor, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said output terminal thereof; and
wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said input terminal thereof, and a sixth transistor which has a first electrode coupling with said second node, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said output terminal thereof.
6. The semiconductor device in accordance with claim 1, wherein said start-up circuit comprises;
a third node;
a capacitance element which is coupled between said third node and said second node;
a resistor which is coupled with said first node;
a first switch which has an ON state and an OFF state, and which is coupled between said first node and said input terminal of said second current mirror circuit; and
a second switch which has an ON state and an OFF state, and which is coupled between said resistor and said third node.
7. The semiconductor device in accordance with claim 6, wherein said first switch comprises a first transistor which has a control electrode coupling with said third node, a first electrode coupling with said first node and a second electrode coupling with said input terminal of said second current mirror circuit, and wherein said second switch comprises a second transistor which has a control electrode coupling with said input terminal of said first current mirror circuit, a first electrode coupling with said resistor and a second electrode coupling with said third node.
8. The semiconductor device in accordance with claim 7, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said input terminal thereof, and a fourth transistor which has a first electrode coupling with said first node, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said output terminal thereof; and wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said input terminal thereof, and a sixth transistor which has a first electrode coupling with said second node through a resistor, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said output terminal thereof.
9. The semiconductor device in accordance with claim 7, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said input terminal thereof, and a fourth transistor which has a first electrode coupling with said first node through a resistor, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said output terminal thereof; and
wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said input terminal thereof, and a sixth transistor which has a first electrode coupling with said second node, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said output terminal thereof.
10. A semiconductor device, comprising:
a first node which is provided a first voltage;
a second node which is provided a second voltage, wherein said second voltage is lower than said first voltage;
a first current mirror circuit which has an input terminal and an output terminal, wherein said first current mirror circuit is coupled with said first node;
a second current mirror circuit which has an input terminal and an output terminal, wherein said input terminal of said second current mirror circuit is coupled with said output terminal of said first current mirror circuit, wherein said output terminal of said second current mirror circuit is coupled with said input terminal of said first current mirror circuit and wherein said second current mirror circuit is coupled with said second node;
a start-up circuit which supplies current to said input terminal of said first current mirror circuit based on voltage on said input terminal of said second current mirror circuit.
11. The semiconductor device in accordance with claim 10, wherein said start-up circuit comprises;
a third node;
a capacitance element which is coupled between said first node and said third node;
a first switch which has an ON state and an OFF state, and which is coupled between said second node and said input terminal of said first current mirror circuit; and
a second switch which has an ON state and an OFF state, and which is coupled between said second node and said third node.
12. The semiconductor device in accordance with claim 11, wherein said first switch comprises a first transistor which has a control electrode coupling with said third node, a first electrode coupling with said second node and a second electrode coupling with said input terminal of said first current mirror circuit, and wherein said second switch comprises a second transistor which has a control electrode coupling with said input terminal of said second current mirror circuit, a first electrode coupling with said second node and a second electrode coupling with said third node.
13. The semiconductor device in accordance with claim 12, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said input terminal thereof, and a fourth transistor which has a first electrode coupling with said first node, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said output terminal thereof; and wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said input terminal thereof, and a sixth transistor which has a first electrode coupling with said second node through a resistor, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said output terminal thereof.
14. The semiconductor device in accordance with claim 12, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said input terminal thereof, and a fourth transistor which has a first electrode coupling with said first node through a resistor, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said output terminal thereof; and
wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said input terminal thereof, and a sixth transistor which has a first electrode coupling with said second node, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said output terminal thereof.
15. A semiconductor device, comprising:
a first node which is provided a first voltage;
a second node which is provided a second voltage, wherein said second voltage is lower than said first voltage;
a first current mirror circuit which is coupled with said first node;
a second current mirror circuit which is coupled with said second node, wherein said second current mirror circuit is coupled with said first current mirror circuit through a third node and a fourth node;
a start-up circuit which supplies current to said fourth node based on voltage on said third node.
16. The semiconductor device in accordance with claim 15, wherein said start-up circuit comprises;
a fifth node;
a capacitance element which is coupled between said fifth node and said second node;
a first switch which has an ON state and an OFF state, and which is coupled between said first node and said fourth node; and
a second switch which has an ON state and an OFF state, and which is coupled between said first node and said fifth node.
17. The semiconductor device in accordance with claim 16, wherein said first switch comprises a first transistor which has a control electrode coupling with said fifth node, a first electrode coupling with said first node and a second electrode coupling with said fourth node, and
wherein said second switch comprises a second transistor which has a control electrode coupling with said third node, a first electrode coupling with said first node and a second electrode coupling with said fifth node.
18. The semiconductor device in accordance with claim 17, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said third node, and a fourth transistor which has a first electrode coupling with said first node, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said fourth node; and
wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said fourth node, and a sixth transistor which has a first electrode coupling with said second node through a resistor, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said third node.
19. The semiconductor device in accordance with claim 17, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said third node, and a fourth transistor which has a first electrode coupling with said first node through a resistor, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said fourth node; and wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said fourth node, and a sixth transistor which has a first electrode coupling with said second node, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said third node.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for estimating error in measured data from a controlled-source electromagnetic survey of a subsurface region, comprising:
(a) selecting data from the electric or magnetic field survey data, said selected data corresponding to a plurality of different offsets (source-receiver spacings) and to a selected single frequency in the source’s signal’s frequency spectrum;
(b) generating a geo-electric model of the subsurface region, said model including at least resistivity or conductivity as a function of position in the region;
(c) solving electromagnetic field equations to simulate the survey’s electromagnetic responses for said selected frequency and for source and receiver locations corresponding to said selected data, using the geo-electric model of the subsurface region and survey source parameters;
(d) selecting a near-zero offset range; and
(e) estimating data error at all offsets by comparing measured survey data to simulated data at least one offset within said selected range of near-zero offsets, said estimated error providing a means for correcting measured data.
2. The method of claim 1, wherein the survey data obtained are phase data.
3. The method of claim 1, wherein the survey data obtained are amplitude data.
4. The method of claim 1, wherein the error is estimated by data fitting in a selected norm such as least-squares for at least one offset within said selected range of near-zero offsets.
5. The method of claim 1, wherein said geo-electric model also includes at least one of a group consisting of complex conductivity, permeability and permittivity, each as a function of position in the subsurface region.
6. The method of claim 2, wherein the estimating data error step results in a single phase shift which can be applied to correct measured phase data.
7. The method of claim 3, wherein the estimating data error step results in a single amplitude scale factor which can be applied to correct measured amplitude data.
8. The method of claim 1, further comprising repeating steps (a)-(e) for all source and receiver locations in the survey and for all frequencies in the source’s frequency spectrum having associated amplitude within a pre-selected range.
9. The method of claim 8, wherein the same geo-electric model is used for each repetition of steps (a)-(e).
10. The method of claim 1, further comprising plotting measured and simulated data vs. offset and using the plot to select the near-zero offset range and to estimate the data error over said range.
11. The method of claim 1, wherein the near-zero offset range is from about \u22122 km to about +2 km but excluding a near-zero sub-range determined based on observation of receiver saturation effects within said sub-range.
12. The method of claim 1, wherein said geo-electric model and said simulation of electromagnetic responses are three dimensional.
13. The method of claim 1, wherein said selected survey data are recorded at a single receiver location.
14. The method of claim 1, wherein said selected survey data correspond to a single source location.
15. A method for producing hydrocarbons from a subsurface region, comprising:
(a) performing a controlled-source electromagnetic survey of the subsurface region;
(b) obtaining data from said survey, corrected for error by the method of claim 1;
(c) using the corrected data to identify a layer showing a resistivity anomaly indicating presence of hydrocarbons; and
(d) drilling a well into said anomalous layer and producing hydrocarbons.
16. The method of claim 15, wherein the survey data corrected are phase data.
17. The method of claim 15, wherein the survey data corrected are amplitude data.