1. A Multiply-Accumulate (MAC) processor machine comprising:
an input interface configured to receive a number N of data symbols, the number N of data symbols being a power of 2;
a number of multiply-accumulate (MAC) blocks, each MAC block configured to, in response to receiving a pair of data symbols, execute a butterfly algorithm to generate a corresponding pair of intermediate results by calculating complex products and sums using the received pair of data symbols and twiddle factors;
a memory configured to store the N received data symbols, the twiddle factors, and the intermediate results of the butterfly algorithm; and
a configurable instruction set digital signal processor core configured to:
select and read at least one pair of the N received data symbols to read from a location in the memory,
input each of the selected pair of the N received data symbols to the MAC blocks,
write, to the location, the intermediate results the MAC blocks generated using the selected at least one pair of the N received data symbols, and
output N binary symbols, each binary symbol corresponding to an order of the output and corresponding to a bit-reversal of a corresponding input from the selected pair of received data symbols.
2. The MAC processor machine as set forth in claim 1, wherein a subset of the MAC blocks are arranged in a sequence of processing stages, the sequence of stages comprising log(N) stages and N multiplications in each stage, and each subset of the MAC blocks comprising
log
2
\ue8a0
(
N
)
\xd7
N
2
MAC blocks per stage.
3. The MAC processor machine as set forth in claim 2, wherein the configurable instruction set digital signal processor core is further configured to:
input the N received data symbols to the subset of the MAC blocks of a first stage of the sequence of stages;
in response to generating N intermediate results from the first stage, inputting the N intermediate results from the first stage to the subset of MAC blocks of a second stage of the sequence of stages.
4. The MAC processor machine as set forth in claim 3, wherein the configurable instruction set digital signal processor core is further configured to determine that the first stage is an antepenultimate stage of the sequence of stages; and
wherein the MAC processor further comprises a hardware accelerator configured to receive intermediate results of the antepenultimate stage, perform a last two stages of the sequence of stages in parallel with performing a first two stages of the sequence of stages using a subsequent set of input data symbols,
wherein a penultimate stage of the sequence of stages is configured to output a complex complement of the intermediate results of the antepenultimate stage, and
wherein a last stage of the sequence of stages is configured to output a negative of the intermediate results of the penultimate stage.
5. The MAC processor machine as set forth in claim 4, wherein the output of the last stage is coupled to an output reorderer configured to perform a bit reversal of the results of the last stage.
6. The MAC processor machine as set forth in claim 1, wherein the configurable instruction set digital signal processor core comprises a very long instruction word (VLIW) configured to control switches independently to input each of the selected pair of the N received data symbols to the MAC blocks.
7. The MAC processor machine as set forth in claim 1, wherein the configurable instruction set digital signal processor core comprises a single instruction multiple data (SIMD) configured to control switches that are partly dependent upon a status of each other to input each selected pair of the N received data symbols to the MAC blocks.
8. The MAC processor as set forth in claim 1, wherein the memory comprises an array or rows and columns, the array comprising:
one column configured to store the N data symbols in ascending order;
a number of stage columns corresponding to a sequence of processing stages, each stage columns configured to store a set of twiddle factors for the corresponding processing stage; and
a number of memory blocks, each memory block comprising two consecutive rows of the array, wherein the number of memory blocks is
N
2
.
9. The MAC processor as set for in claim 1, wherein the configurable instruction set digital signal processor core is further configured to execute at least one of:
a Fast Fourier Transform (FFT) process,
a Finite Impulse Response (FIR) filter process,
an Infinite Impulse Response (IIR) filter process, and
a digital filter process.
10. A Fast Fourier Transform (FFT) context-based reconfigurable instruction set processor (CRISP) machine for performing a FFT process, the FFT CRISP machine comprising:
an input interface configured to receive a number N of data symbols, the number N of data symbols being a power of 2;
a number of multiply-accumulate (MAC) blocks, each MAC block configured, to in response to receiving a pair of data symbols, execute a butterfly algorithm to generate a corresponding pair of intermediate results by calculating complex products and sums using the received pair of data symbols and twiddle factors; and
a memory configured to store the N received data symbols, the twiddle factors, and the intermediate results of the butterfly algorithm; and
a configurable instruction set digital signal processor core configured to execute the FFT process by:
selecting and read at least one pair of the N received data symbols to read from a location in the memory,
inputting each of the selected pair of the N received data symbols to the MAC blocks,
writing, to the location, the intermediate results the MAC blocks generated using the selected at least one pair of the N received data symbols, and
outputting N binary symbols as a FFT of the received N data symbols, each binary symbol corresponding to an order of the output and corresponding to a bit-reversal of a corresponding input from the selected pair of received data symbols.
11. The FFT CRISP machine as set forth in claim 10, wherein a subset of the MAC blocks are arranged in a sequence of FFT computation stages, the sequence of FFT computation stages comprising log(N) stages and N multiplications in each stage, and each subset of the MAC blocks comprising
log
2
\ue8a0
(
N
)
\xd7
N
2
MAC blocks per stage.
12. The FFT CRISP machine as set forth in claim 11 wherein the configurable instruction set digital signal processor core is further configured to:
input the N received data symbols to the subset of the MAC blocks of a first stage of the sequence of FFT computation stages;
in response to generating N intermediate results from the first stage, inputting the N intermediate results from the first stage to the subset of MAC blocks of a second stage of the sequence of stages.
13. The FFT CRISP machine as set forth in claim 12, wherein the configurable instruction set digital signal processor core is further configured to determine that the first stage is an antepenultimate stage of the sequence of FFT computation stages; and
wherein the FFT CRISP further comprises a hardware accelerator configured to receive intermediate results of the antepenultimate stage, perform a last two stages of the sequence of FFT computation stages in parallel with performing a first two stages of the sequence of stages using a subsequent set of input data symbols,
wherein a penultimate stage of the sequence of stages is configured to output a complex complement of the intermediate results of the antepenultimate stage, and
wherein a last stage of the sequence of stages is configured to output a negative of the intermediate results of the penultimate stage.
14. The FFT CRISP machine as set forth in claim 13, wherein the output of the last stage is coupled to an output reorderer configured to perform a bit reversal of the results of the last stage.
15. The FFT CRISP machine as set forth in claim 10, wherein the configurable instruction set digital signal processor core comprises a very long instruction word (VLIW) configured to control switches independently to input each of the selected pair of the N received data symbols to the MAC blocks.
16. The FFT CRISP machine as set forth in claim 10, wherein the configurable instruction set digital signal processor core comprises a single instruction multiple data (SIMD) configured to control switches that are partly dependent upon a status of each other to input each selected pair of the N received data symbols to the MAC blocks.
17. The FFT CRISP as set forth in claim 10, wherein the memory comprises an array or rows and columns, the array comprising:
one column configured to store the N data symbols in ascending order;
a number of stage columns corresponding to a sequence of processing stages, each stage columns configured to store a set of twiddle factors for the corresponding processing stage; and
a number of memory blocks, each memory block comprising two consecutive rows of the array, wherein the number of memory blocks is
N
2
.
18. A method of computing a Fast Fourier Transform (FFT) of data symbols inputted to a FFT context-based reconfigurable instruction set processor (CRISP) machine, the method comprising:
receiving a number N of the data symbols into an input interface of the FFT CRISP machine, the number N being a power of 2;
in response to receiving a pair of data symbols by a number of multiply-accumulate (MAC) blocks, executing a butterfly algorithm to generate a corresponding pair of intermediate results by calculating complex products and sums using the received pair of data symbols and twiddle factors; and
storing the N received data symbols, the twiddle factors, and the intermediate results of the butterfly algorithm in a memory;
selecting and reading, by a configurable instruction set digital signal processor core, at least one pair of the N received data symbols to read from a location in the memory,
inputting each of the selected pair of the N received data symbols to the MAC blocks,
writing, to the location, the intermediate results the MAC blocks generated using the selected at least one pair of the N received data symbols, and
outputting N binary symbols, each binary symbol corresponding to an order of the output and corresponding to a bit-reversal of a corresponding input from the selected pair of received data symbols.
19. The method as set forth in claim 18, wherein a subset of the MAC blocks are arranged in a sequence of processing stages, the sequence of stages comprising log(N) stages and N multiplications in each stage, and each subset of the MAC blocks comprising
log
2
\ue8a0
(
N
)
\xd7
N
2
MAC blocks per stage.
20. The method as set forth in claim 19, further comprising:
inputting the N received data symbols to the subset of the MAC blocks of a first stage of the sequence of stages;
in response to generating N intermediate results from the first stage, inputting the N intermediate results from the first stage to the subset of MAC blocks of a second stage of the sequence of stages.
21. The method as set forth in claim 20, further comprising:
in response to determining that the first stage is an antepenultimate stage of the sequence of stages, receiving intermediate results of the antepenultimate stage by a hardware accelerator of the FFT CRISP;
performing, by the hardware accelerator, a last two stages of the sequence of stages in parallel with performing a first two stages of the sequence of stages using a subsequent set of input data symbols,
wherein a penultimate stage of the sequence of stages is configured to output a complex complement of the intermediate results of the antepenultimate stage, and
wherein a last stage of the sequence of stages is configured to output a negative of the intermediate results of the penultimate stage.
22. The method as set forth in claim 20, further comprising
performing, by an output reorderer coupled to receive the output of the last stage, a bit reversal of the results of the last stage.
23. The method as set forth in claim 18, further comprising providing a memory comprising an array or rows and columns, the array comprising:
one column configured to store the N data symbols in ascending order;
a number of stage columns corresponding to a sequence of processing stages, each stage columns configured to store a set of twiddle factors for the corresponding processing stage; and
a number of memory blocks, each memory block comprising two consecutive rows of the array, wherein the number of memory blocks is
N
2
.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A gas sampling system comprising:
a first gas pump that provides a first gas flow at a partial gas vacuum compared to ambient gas pressure;
a second gas pump that provides a second gas flow at a partial gas pressure compared to the ambient gas pressure;
a first orifice that provides said first gas flow;
a plurality of second orifices that provide a plurality of flow members of said second gas flow in a substantially rotational direction that is substantially concentric and both radially and axially external to said first orifice; and
a heater that heats at least one flow member of said second gas flow, wherein the gas sampling system provides the first gas flow for analysis within an ion mobility spectrometer.
2. A gas sampling system as in claim 1 wherein said partial gas vacuum is within 50 millimeters of mercury (50 Torr) of the ambient gas pressure.
3. A gas sampling system as in claim 1 wherein said partial gas pressure is within 50 atmospheres of the ambient gas pressure.
4. A gas sampling system as in claim 1, further comprising:
vanes that cause said second gas flow to flow in a substantially rotational direction.
5. A gas sampling system as in claim 1, further comprising:
a hollow member wherein an inside surface thereof causes said second gas flow to flow in a substantially rotational direction.
6. A gas sampling system, according to claim 5, wherein said heater is disposed within said hollow member.
7. A gas sampling system as in claim 1, wherein the said plurality of second orifices directs the said second gas flow in a substantially perpendicular direction with respect to the axis of the said first orifice.
8. A gas sampling system as in claim 7, further comprising:
a solid surface disposed with its normal axis substantially perpendicular to the axis of the said first orifice, wherein said second gas flow flows in a substantially rotational direction due to the deflection of the flow of at least one flow member by said solid surface.
9. A gas sampling system as in claim 7, wherein said second gas flow flows in a substantially rotational direction due to interaction between the flow members.
10. A gas sampling system as in claim 1, further comprising:
a rotating impeller that causes said second gas flow to flow in a substantially rotational direction.
11. A gas sampling system as in claim 1 wherein said rotational direction of all the flow members is mutually clockwise or mutually counter-clockwise relative to the axis of said first orifice.
12. A gas sampling system as in claim 1 wherein the heat for said heater is provided by at least one of electric current resistance or impedance, photon radiation, fluid compression, Peltier effect, and chemical flame or reaction.
13. A gas sampling system as in claim 1 wherein said heater uses waste heat generated by other components of said ion mobility spectrometer.
14. A gas sampling system as in claim 1 wherein said heater increases temperature of said second gas flow from said plurality of second orifices by at least 10 degrees Centigrade from ambient temperature.
15. A gas sampling system, according to claim 1, wherein said heater is a radiative heater.
16. A gas sampling system, according to claim 1, further comprising:
tubulation that couples said second gas pump with said second orifaces.
17. A gas sampling system, according to claim 16, wherein said heater is disposed outside said tubulation.
18. A gas sampling system, according to claim 16, wherein said heater is disposed inside said tubulation.
19. A gas sampling system, according to claim 16, wherein said heater is disposed in series with said tubulation.
20. A gas sampling system, according to claim 1, wherein said heater is disposed within said second orifices.
21. A gas sampling system comprising:
a first gas pump that provides a first gas flow at a partial gas vacuum compared to ambient gas pressure;
a second gas pump that provides a second gas flow at a partial gas pressure compared to the ambient gas pressure;
a first orifice that provides said first gas flow;
a plurality of second orifices that provide a plurality of flow members of said second gas flow in a substantially rotational direction that is substantially concentric and both radially and axially external to said first orifice; and at least one chemical addition into at least one flow member, wherein the gas sampling system provides the first gas flow for analysis within an ion mobility spectrometer.
22. A gas sampling system as in claim 21 wherein said partial gas vacuum is within 50 millimeters of mercury (50 Torr) of the ambient gas pressure.
23. A gas sampling system as in claim 21 wherein said partial gas pressure is within 50 atmospheres of the ambient gas pressure.
24. A gas sampling system as in claim 21, further comprising:
vanes that cause said second gas flow to flow in a substantially rotational direction.
25. A gas sampling system as in claim 21, further comprising:
a hollow member wherein an inside surface thereof cause said second gas flow to flow in a substantially rotational direction.
26. A gas sampling system as in claim 21, wherein the said plurality of second orifices directs the said second gas flow in a substantially perpendicular direction with respect to an axis of the said first orifice.
27. A gas sampling system as in claim 26, further comprising:
a solid surface disposed with its normal axis substantially perpendicular to the axis of the said first orifice, wherein said second gas flow flows in a substantially rotational direction due to the deflection of the flow of at least one flow member by said solid surface.
28. A gas sampling system as in claim 26, wherein said second gas flow flows in a substantially rotational direction due to interaction between the flow members.
29. A gas sampling system as in claim 21, further comprising:
a rotating impeller that causes said second gas flow to flow in a substantially rotational direction.
30. A gas sampling system as in claim 21 wherein said rotational direction of all the flow members is mutually clockwise or mutually counter-clockwise relative to the axis of said first orifice.
31. A gas sampling system as in claim 21 wherein said chemical addition is water in liquid or vapor form.
32. A gas sampling system as in claim 21 wherein said chemical addition is at least one of acetone, alcohol, ethylene glycol, and propylene glycol.