1. A semiconductor memory comprising:
first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns;
a first cell block which is disposed in the first column;
a first block select transistor which is connected between the first or second bit line and one end of the first cell block;
a second cell block which is disposed in the second column; and
a second block select transistor which is connected between the second or first bit line and one end of the second cell block,
wherein the twisting of the first and second bit lines is carried out at a block selector region in which the first and second block select transistors are disposed.
2. The semiconductor memory according to claim 1,
wherein the first and second cell blocks each are composed of a plurality of cell units connected in series, and said plurality of cell units each are composed of a MOS transistor and a ferroelectric capacitor connected in parallel.
3. The semiconductor memory according to claim 1,
wherein the twisting of the first and second bit lines is carried out by using wiring in a second wiring layer different from a first wiring layer in which the first and second bit lines are disposed.
4. The semiconductor memory according to claim 3,
wherein the second wiring layer is a wiring layer in which block select lines connected to the first and second block select transistors are disposed.
5. The semiconductor memory according to claim 1,
wherein the first cell block is connected to the first bit line, and the second cell block is connected to the second bit line.
6. The semiconductor memory according to claim 1,
wherein the first cell block is connected to the second bit line, and the second cell block is connected to the first bit line.
7. The semiconductor memory according to claim 1,
wherein at least one bit line contact portion is disposed in the constant period.
8. A semiconductor memory comprising:
first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns;
a first cell block which is disposed in the first column;
a first block select transistor which is connected between the first or second bit line and one end of the first cell block;
a first plate line which is connected to the other end of the first cell block;
a second cell block which is disposed in the second column;
a second block select transistor which is connected between the second or first bit line and one end of the second cell block; and
a second plate line which is connected to the other end of the second cell block,
wherein the twisting of the first and second bit lines is carried out at a plate line region in which the first and second plate lines are disposed.
9. The semiconductor memory according to claim 8,
wherein the first and second cell blocks each are composed of a plurality of cell units connected in series, and said plurality of cell units each are composed of a MOS transistor and a ferroelectric capacitor connected in parallel.
10. The semiconductor memory according to claim 8,
wherein the twisting of the first and second bit lines is carried out by using wiring in a second wiring layer different from a first wiring layer in which the first and second bit lines are disposed.
11. The semiconductor memory according to claim 10,
wherein the second wiring layer is a wiring layer in which block select lines connected to the first and second block select transistors are disposed.
12. The semiconductor memory according to claim 8,
wherein the first cell block is connected to the first bit line, and the second cell block is connected to the second bit line.
13. The semiconductor memory according to claim 8,
wherein the first cell block is connected to the second bit line, and the second cell block is connected to the first bit line.
14. The semiconductor memory according to claim 8,
wherein at least one bit line contact portion is disposed in the constant period.
15. A semiconductor memory comprising:
first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns;
a plurality of first memory cells which are disposed in the first column; and
a plurality of second memory cells which are disposed in the second column,
wherein the first bit line is only connected to said plurality of first memory cells, and the second bit line is only connected to said plurality of second memory cells.
16. The semiconductor memory according to claim 15,
wherein, when the first bit line is disposed in the second column, the first bit line is connected to said plurality of first memory cells by using wiring in a second wiring layer different from a first wiring layer in which the first and second bit lines are disposed, and when the second bit line is disposed in the first column, the second bit line is connected to said plurality of second memory cells by using wiring in the second wiring layer.
17. The semiconductor memory according to claim 15,
further comprising:
a first block select transistor which is connected between the first bit line and one end of the first memory cell;
a second block select transistor which is connected between the second bit line and one end of the second memory cell;
a first plate line which is connected to the other end of the first memory cell; and
a second plate line which is connected to the other end of the second memory cell.
18. The semiconductor memory according to claim 17,
wherein the twisting of the first and second bit lines is carried out at a block selector region in which the first and second block select transistors are disposed, or a plate line region in which the first and second plate lines are disposed.
19. The semiconductor memory according to claim 17,
wherein the first and second memory cells each are composed of a MOS transistor and a ferroelectric capacitor connected in parallel.
20. The semiconductor memory according to claim 15,
wherein at least one bit line contact portion is disposed in the constant period.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for storing operational information in an array of memory cells, comprising:
storing data units of operational information in memory cells of at least one row of a first block of memory cells; and
storing the data units in memory cells of at least one row of a second block of memory cells, wherein an order of the data units stored in the at least one row of the second block is different than an order of the data units stored in memory cells of the at least one row of the first block.
2. The method of claim 1, wherein the order of the data units stored in the at least one row of the second block is different such that a particular data unit stored in a memory cell coupled to a column in the first block is stored in a memory cell coupled to a different column in the second block.
3. The method of claim 1, wherein the order of the data units stored in the at least one row of the second block is different such that all data units stored in memory cells coupled to columns in the first block are stored in memory cells coupled to different columns in the second block.
4. The method of claim 17 wherein the order of the data units stored in the at least one row of the second block is different such that columns coupled to memory cells storing one or more data units in the first block are coupled to memory cells not storing data units in the second block.
5. The method of claim 1, wherein the method includes storing the data units in more than two blocks.
6. The method of claim 5, wherein the method includes storing the data units in adjacent data blocks.
7. The method of claim 1, wherein the method includes storing a copy of an inverse of the data units in memory cells of the at least one row of the first block.
8. The method of claim 7, wherein the method includes storing a copy of the inverse of the data units in memory cells of the at least one row of the second block in a different order than an order in which the copy of the inverse of the data units is stored in the first block.
9. A method for storing operational information in an array of memory cells, comprising:
storing operational information in a sequential order in successive memory cells coupled by a first select line, beginning with a memory cell coupled by a first sense line; and
storing the copied operational information in the sequential order in successive memory cells coupled by a second select line, beginning with a memory cell coupled by a second sense line.
10. The method of claim 9, wherein the method includes storing operational information on the first select line located in a first block and on the second select line located in a second block, adjacent to the first block.
11. The method of claim 9, wherein the method includes storing a copy of operational information in the sequential order in successive memory cells coupled by multiple select lines, each copy beginning with a memory cell coupled by a different sense line.
12. The method of claim 11, wherein the method includes sensing the data in accordance with a hierarchical sensing order.
13. The method of claim 9, wherein the method includes storing copied operational information beginning with a memory cell coupled by the second select line, wherein none of the successive memory cells storing operational information on the first select line share a sense line with any of the successive memory cells storing copied operational information on the second select line.
14. A memory device, comprising:
an array of memory cells, wherein a first number of memory cells constitute a page, and a second number of memory cells constitute a block;
a first block and a second block dedicated to storing operational information, wherein the first block and the second block each have a different data pattern; and
control circuitry coupled to the array, wherein the control circuitry is operable to sense the first block and the second block.
15. The device of claim 14, wherein the second block is dedicated to storing a copy of operational information stored in the first block.
16. The device of claim 15, wherein the control circuitry is operable to sense the second block when the first block contains an error.
17. The device of claim 14, wherein operational information stored in the first block and the second block is stored in at least one page per block.
18. The device of claim 17, wherein the at least one page per block stores a set of operational information and a copy thereof.
19. The device of claim 18, wherein the set of operational information is selected from the group including:
column redundancy data;
block redundancy data;
die identifiers;
functionality trim data;
bandgap data; and
fuse trim data.
20. The device of claim 14, wherein memory cells in pages not used for storing operational information in the first block and second block remain in an erased state.
21. The device of claim 14, wherein the device includes an array of memory cells arranged in a single plane.
22. The device of claim 14, wherein the device includes arrays of memory cells arranged in at least two planes.
23. A memory device, comprising:
an array of memory cells, wherein a number of cells are coupled to one of a number of select lines and wherein a number of cells are coupled to one of a number of sense lines; and
wherein operational information is stored in an arrangement within the cells coupled to a first select line and wherein the operational information is stored in a different arrangement within the cells coupled to a second select line.
24. The device of claim 23, wherein the different arrangement is the arrangement in which the information is stored on the first select line shifted by a number of columns.
25. The device of claim 24, wherein the arrangement is shifted by a number of columns sufficient to prevent information and copied information from being stored in memory cells coupled to a common sense line.