1. A semiconductor device comprising:
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type on the first semiconductor region;
a third semiconductor region of the first conductivity type on the second semiconductor region;
a control electrode disposed within the first and second semiconductor regions;
an insulating film between the control electrode and the first and second semiconductor regions;
a first electrode electrically connected with the second semiconductor region and the third semiconductor region;
a second electrode; and
a fourth semiconductor region of the second conductivity type between the second electrode and the first semiconductor region and electrically connected with the second electrode, the fourth semiconductor region including a first portion having a first dopant concentration and a second portion having a second dopant concentration higher than the first dopant concentration, wherein an area of contact of the first portion with the second electrode is larger than an area of contact of the second area with the second electrode.
2. The semiconductor device according to claim 1, wherein when an electric current smaller than a saturation current flows between the first electrode and the second electrode, carriers are injected into the first semiconductor region mostly from the first portion, and
when the saturation current flows between the first electrode and the second electrode, the carriers are injected into the first semiconductor region from the first portion and the second portion.
3. The semiconductor device according to claim 2, wherein a relationship S2(S1+S2)\u2266IrcIsc is satisfied, where S1 represents the first contact area, S2 represents the second contact area, Irc represents a rated current of the semiconductor device, and Isc represents a saturation current of the semiconductor device.
4. The semiconductor device according to claim 3, wherein S2(S1+S2) is equal to or smaller than \u2155.
5. The semiconductor device according to claim 4, wherein
the first dopant concentration is equal to or higher than 1\xd71016 cm\u22123 and equal to or lower than 1\xd71018 cm\u22123, and
the second dopant concentration is equal to or higher than 1\xd71018 cm\u22123 and equal to or lower than 1\xd71020 cm\u22123.
6. The semiconductor device according to claim 5, wherein
the first portion has a longer length in a first direction along a contact surface with the second electrode than the second portion.
7. The semiconductor device according to claim 6, wherein
W2(W1+W2) is equal to or smaller than \u2155, where W1 represents the length of the first portion and W2 represents the length of the second portion.
8. The semiconductor device according to claim 7, wherein the length of the second portion is equal to or larger than 0.1 micrometers and equal to or smaller than 10 micrometers.
9. The semiconductor device according to claim 1, further comprising:
a fifth semiconductor region of the first conductivity type between the first semiconductor region and the fourth semiconductor region, the fifth semiconductor region having a higher dopant concentration than the first semiconductor region.
10. The semiconductor device according to claim 1, wherein the control electrode extends between a lower portion of the first semiconductor region and an upper portion of the third semiconductor region and is insulated from the first, second, and third semiconductor region by an insulating layer.
11. A semiconductor device comprising:
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type on the first semiconductor region;
a third semiconductor region of the first conductivity type on the second semiconductor region;
a control electrode disposed within the first and second semiconductor regions;
an insulating film between the control electrode and the first and second semiconductor regions;
a first electrode electrically connected with the second semiconductor region and the third semiconductor region;
a second electrode; and
a fourth semiconductor region of the second conductivity type between the second electrode and the first semiconductor region and electrically connected with the second electrode, the fourth semiconductor region including first and second portions arranged along a first direction, the first portion having a first dopant concentration and the second portion having a second dopant concentration higher than the first dopant concentration and a shorter length in the first direction than the first portion.
12. The semiconductor device according to claim 11, wherein
the first dopant concentration is equal to or higher than 1\xd71016 cm\u22123 and equal to or lower than 1\xd71018 cm\u22123, and
the second dopant concentration is equal to or higher than 1\xd71018 cm\u22123 and equal to or lower than 1\xd71020 cm\u22123.
13. The semiconductor device according to claim 12, wherein
W2(W1+W2) is equal to or smaller than \u2155, where W1 represents the length of the first portion and W2 represents the length of the second portion.
14. The semiconductor device according to claim 11, further comprising:
a fifth semiconductor region of the first conductivity type between the first semiconductor region and the fourth semiconductor region, the fifth semiconductor region having a higher dopant concentration than the first semiconductor region.
15. A semiconductor device comprising:
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type on the first semiconductor region;
a third semiconductor region of the first conductivity type on the second semiconductor region;
a control electrode disposed within the first and second semiconductor regions;
an insulating film between the control electrode and the first and second semiconductor regions;
a first electrode electrically connected with the second semiconductor region and the third semiconductor region;
a second electrode; and
a fourth semiconductor region of the second conductivity type between the second electrode and the first semiconductor region and electrically connected with the second electrode, the fourth semiconductor region including a first portion having a first dopant concentration and a second portion having a second dopant concentration higher than the first dopant concentration, wherein an area of contact of the first portion with the second electrode is larger than an area of contact of the second area with the second electrode, and a height of the first portion in a direction that extends from the second electrode to the first electrode is smaller than a height of the second portion in the same direction.
16. The semiconductor device according to claim 15, wherein
the first dopant concentration is equal to or higher than 1\xd71016 cm\u22123 and equal to or lower than 1\xd71018 cm\u22123, and
the second dopant concentration is equal to or higher than 1\xd71018 cm\u22123 and equal to or lower than 1\xd71020 cm\u22123.
17. The semiconductor device according to claim 16, wherein
W2(W1+W2) is equal to or smaller than \u2155, where W1 represents a length of the first portion in a direction along a contact surface with the second electrode and W2 represents a length of the second portion in a direction along a contact surface with the second electrode.
18. The semiconductor device according to claim 15, further comprising:
a fifth semiconductor region of the first conductivity type between the first semiconductor region and the fourth semiconductor region, and the fifth semiconductor region having a higher dopant concentration than the first semiconductor region.
19. The semiconductor device according to claim 18, wherein the first portion is in contact with the fifth semiconductor region and the second portion is not in contact with the fifth semiconductor region.
20. The semiconductor device according to claim 15, wherein the first portion is in contact with the first semiconductor region and the second portion is not in contact with the first semiconductor region.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for directly growing a non-Ga-polar surface of gallium nitride (GaN), comprising:
placing a seed crystal of GaN having an exposed non-Ga-polar surface of GaN into an autoclave;
placing a mineralizer into the autoclave;
placing a source into the autoclave;
adding ammonia to the autoclave;
heating the autoclave; and
ammonothermally growing the GaN in the heated autoclave, using the mineralizer, source and ammonia, wherein the exposed non-Ga-polar surface of the GaN is smoother than a Ga-polar surface of the GaN.
2. The method of claim 1, wherein the mineralizer is selected from a group comprising NaNH2, KNH2, LiNH2, NH4Cl, NH4Br, and NH4I.
3. The method of claim 1, wherein the source comprises polycrystalline GaN.
4. The method of claim 1, wherein the autoclave is heated in zones.
5. The method of claim 4, wherein a first zone is heated to a first temperature and a second zone is heated to a second temperature.
6. The method of claim 5, wherein the source is placed in the first zone and the seed crystal of GaN having the exposed non-Ga polar surface of GaN is placed in the second zone.
7. The method of claim 6, wherein the non-Ga polar surface is an N-polar C-plane (000-1) surface.
8. The method of claim 6, wherein the non-Ga polar surface is an M-plane {10-10} surface.
9. The method of claim 6, wherein the non-Ga polar surface is an A-plane {11-20} surface.
10. The method of claim 6, wherein the non-Ga polar surface is a {10-11} surface.
11. The method of claim 6, wherein the non-Ga polar surface is a {10-1-1} surface.
12. The method of claim 6, wherein the non-Ga polar surface is a {11-22} surface.
13. The method of claim 6, wherein the non-Ga polar surface is a {11-2-2} surface.
14. The method of claim 1, wherein the source comprises Ga metal.
15. A method of fabricating a gallium nitride (GaN) substrate, comprising:
ammonothermally growing a GaN substrate resulting in an exposed N-polar (N-face) or M-plane surface that is smoother than a Ga-polar (Ga-face) surface of the GaN substrate.
16. The method of claim 15, wherein the N-polar (N-face) or M-plane surface is smooth enough for growth of device layers.
17. The method of claim 16, wherein the N-polar (N-face) or M-plane surface is smooth enough for direct growth of device layers.
18. The method of claim 17, wherein the N-polar (N-face) or M-plane surface is smooth enough for direct growth of device layers without subsequent processing.
19. A method of fabricating an opto-electronic device comprising:
fabricating a GaN substrate from a GaN bulk crystal grown ammonothermally on a GaN seed, wherein a growth surface of the GaN bulk crystal is not a Ga-polar surface and the growth surface as grown is smoother than a Ga-polar surface; and
growing one or more group III nitride layers on the growth surface of the GaN substrate.
20. The method of claim 19, wherein the growing step comprises:
growing a plurality of n-type group III nitride layers on the growth surface;
growing at least one group III nitride light-emitting active layer on the plurality of n-type group III nitride layers; and
growing at least one p-type group III nitride layer having an Mg doping on the active layers.
21. The method of claim 20, wherein an Mg concentration of the Mg-doped layer is more than 1021cm\u22123.
22. The method of claim 19, wherein the growth surface is an M-plane {10-10} surface.
23. The method of claim 19, wherein the growth surface is an A-plane {11-20} surface.
24. The method of claim 19, wherein the growth surface is a {10-11} surface.
25. The method of claim 19, wherein the growth surface is a {10-1-1} surface.
26. The method of claim 19, wherein the growth surface is a {11-22} surface.
27. The method of claim 19, wherein the growth surface is a {11-2-2} surface.
28. The method of claim 19, wherein the growth surface is a {20-21} surface.
29. A method for fabricating a GaN layer, comprising:
utilizing an N-polar surface or an M-plane surface of the GaN layer as a growth surface, wherein the N-polar surface or the M-plane surface is prepared using an ammonothermal growth technique.
30. The method of claim 29, further comprising growing one or more group-III nitride layers to the N-polar or M-plane surface of the GaN layer.
31. A method for growing a group-III nitride layer, comprising:
ammonothermally growing a group-III nitride layer on a substrate, wherein the group-III nitride layer comprises an N-face of a C-plane (000-1) or a M-plane {10-10} that is directly exposed as a result of the growth of the group-III nitride layer.
32. The method of claim 31, wherein the N-face of the C-plane (000-1) or the M-plane {10-10} is substantially co-planar with a surface of the substrate.
33. The method of claim 31, wherein the N-face of the C-plane (000-1) or the M-plane {10-10} is tilted with respect to a surface of the substrate.
34. The method of claim 31, wherein the N-face of the C-plane (000-1) or the M-plane {10-10} is tilted at an angle less than 10 degrees with respect to the surface of the substrate.
35. The method of claim 31, wherein the N-face of the C-plane (000-1) or the M-plane {10-10} directly accepts growth of at least one additional group-III nitride layer.
36. A method for fabricating a GaN substrate, comprising:
directly growing a GaN substrate with an exposed N-face or M-plane surface that is of device quality using an ammonothermal growth method.
37. The method of claim 36, further comprising growing a group-III nitride layer on the substrate, wherein the group III nitride layer comprises an N-face of a C-plane (000-1) or M-plane {10-10} that is directly exposed as a result of the growth of the group-III nitride layer.
38. The method of claim 36, wherein the N-face or M-plane is substantially co-planar with the plane of the substrate, rather than substantially perpendicular.
39. The method of claim 36, wherein the N-face or M-plane is slightly misaligned with the plane of the substrate.
40. The method of claim 36, wherein the group-III nitride layer directly accepts growth of at least one additional group-III nitride layer.