1. A feed forward amplifier, comprising:
an input for receiving an RF signal;
a main amplifier receiving and amplifying said RF signal;
a main amplifier output sampling coupler;
a first delay coupled to the input and providing a delayed RF signal;
a carrier cancellation combiner coupling the delayed RF signal from the first delay and to the output of the output sampling coupler;
an error amplifier receiving and amplifying the output signal of the carrier cancellation combiner;
a second delay coupled to the output of the main amplifier;
an error coupler combining the output of the error amplifier and a delayed main amplifier output from the second delay so as to cancel distortion introduced by the main amplifier;
an output sampling coupler coupled to the output of the error coupler and providing a sampled output signal;
a carrier signal reduction circuit coupled to the output sampling coupler and providing a reduced carrier sampled output signal with a reduced carrier component; and
a spurious signal detector coupled to the carrier signal reduction circuit, comprising a variable frequency down converter and a digital signal processor, for detecting out of band distortion in the reduced carrier sampled output signal;
wherein the error amplifier has an inherent third delay associated with a signal path and wherein said second delay is substantially less than said third delay.
2. A feed forward amplifier as set out in claim 1, further comprising a controller, coupled to the spurious signal detector, for controlling the feed forward amplifier to minimize distortion detected by the spurious signal detector.
3. A feed forward amplifier as set out in claim 2, further comprising a gain adjuster and phase adjuster coupled between the carrier cancellation combiner and the error amplifier, wherein the controller controls the gain adjuster and phase adjuster to minimize the distortion detected by the spurious signal detector.
4. A feed forward amplifier as set out in claim 2, further comprising a gain adjuster and phase adjuster coupled between the input and the main amplifier, wherein the controller controls the gain adjuster and phase adjuster to minimize the output signal of the carrier cancellation combiner.
5. A feed forward amplifier as set out in claim 2, further comprising a predistorter coupled between the input and the main amplifier, wherein the controller controls the predistorter to minimize the distortion detected by the spurious signal detector.
6. A feed forward amplifier as set out in claim 1, wherein said error amplifier is substantially smaller than said main amplifier.
7. A feed forward amplifier as set out in claim 6, wherein said error amplifier is about one tenth the size of said main amplifier.
8. A feed forward amplifier as set out in claim 1, wherein the reduced carrier sampled output signal provided by said carrier signal reduction circuit has a carrier component about 15\u201320 dB less than the sampled output signal provided by said output sampling coupler.
9. A feed forward amplifier as set out in claim 2, wherein said variable frequency down converter comprises a variable frequency signal generator controlled by said controller and a mixer coupled to receive the variable frequency signal and the reduced carrier sampled output signal, for converting the frequency of the reduced carrier sampled output signal to a lower frequency signal.
10. A feed forward amplifier as set out in claim 9, wherein said spurious signal detector further comprises a bandpass filter coupled to the output of the down converter and wherein said digital signal processor is coupled to the output of the bandpass filter.
11. A feed forward amplifier as set out in claim 10, wherein said spurious signal detector further comprises an analog to digital converter coupled between the bandpass filter and the digital signal processor.
12. A feed forward amplifier, comprising:
an input for receiving an RF signal;
a main amplifier receiving and amplifying said RF signal;
a main amplifier output sampling coupler;
a first delay coupled to the input and providing a delayed RF signal;
a carrier cancellation combiner coupling the delayed RF signal from the first delay and to the output of the output sampling coupler;
an error amplifier receiving and amplifying the output signal of the carrier cancellation combiner;
a second delay coupled to the output of the main amplifier;
an error coupler combining the output the error amplifier and a delayed main amplifier output from the second delay so as to cancel distortion introduced by the main amplifier;
an output sampling coupler coupled to the output of the error coupler and providing a sampled output signal;
a carrier signal reduction circuit coupled to the output sampling coupler and providing a reduced carrier sampled output signal with a reduced carrier component, wherein said carrier signal reduction circuit further comprises an input sampling coupler configured between the first delay and the carrier cancellation combiner for sampling the input RF signal and a second carrier cancellation combiner for combining the sampled output signal and the sampled input RF signal to cancel a carrier component in said sampled output signal; and
a spurious signal detector coupled to the carrier signal reduction circuit, comprising a variable frequency down converter and a digital signal processor, for detecting out of band distortion in the reduced carrier sampled output signal.
13. A feed forward amplifier as set out in claim 12, wherein said carrier signal reduction circuit further comprises an input delay between said input sampling coupler and said second carrier cancellation combiner and an output delay between said output sampling coupler and said second carrier cancellation combiner.
14. A feed forward amplifier as set out in claim 13, wherein said carrier signal reduction circuit further comprises a gain adjuster and phase adjuster coupled between said output sampling coupler and said second carrier cancellation combiner, and wherein the controller controls said gain and phase adjuster to minimize the carrier component of the sampled output signal.
15. A delay mismatched feed forward amplifier, comprising:
an input for receiving an RE input signal;
a first control loop coupled to the input and comprising a main amplifier, a main amplifier output sampling coupler, a delay element, and a first carrier cancellation combiner;
a second control loop coupled to the first control loop and comprising a first signal path receiving the output of the main amplifier, a second signal path comprising an error amplifier receiving the output of the first carrier cancellation combiner, and an error injection coupler coupling the first and second signal paths, said first and second signal paths having a delay mismatch wherein said first signal path has substantially less delay than said second signal path;
an output coupled to the error injection coupler for providing an output signal;
a third control loop coupled between the input and the output and comprising a first coupler for sampling the input signal, a second coupler for sampling the output, and a second carrier cancellation combiner;
a distortion detector coupled to the output signal of the second carrier cancellation combiner, said distortion detector comprising a digital signal processor performing a signal analysis on the output of the second carrier cancellation combiner; and
a controller, coupled to the distortion detector, for controlling at least one of the first and second control loops to minimize distortion detected by the distortion detector.
16. A feed forward amplifier as set out in claim 15, wherein said delay mismatch between said first and second signal paths is greater than 3 cycles of the RF input signal.
17. A feed forward amplifier as set out in claim 15, wherein the delay of the second signal path is about 10\u201320 ns. and the delay of the first signal path is less than about 3 ns.
18. A feed forward amplifier as set out in claim 17, wherein the delay of the second path is about 10 ns. and wherein the delay of the first signal path is about 1.0\u20131.5 ns.
19. A feed forward amplifier as set out in claim 15, wherein the delay of the first signal path is about 30 percent or less of the delay of the second signal path.
20. A feed forward amplifier as set out in claim 15, wherein said third control loop further comprises:
delay means for providing a signal delay equalization of said sampled input signal and said sampled output signal; and
gain and phase adjusting means for providing an amplitude equalization of said sampled output signal and said sampled input signal and an anti-phase addition of the sampled output signal and said sampled input signal at said second carrier cancellation combiner.
21. A feed forward amplifier as set out in claim 20, wherein the controller controls said gain and phase adjusting means to minimize the level of carrier components on the output of the second carrier cancellation combiner.
22. A feed forward amplifier as set out in claim 15, wherein said error amplifier is substantially smaller than said main amplifier.
23. A feed forward amplifier as set out in claim 22, wherein said error amplifier is about one tenth the size of the main amplifier.
24. A feed forward amplifier as set out in claim 15, wherein said RF input signal has a carrier bandwidth of about 5 MHz or less.
25. A feed forward amplifier as set out in claim 15, wherein the output of said second carrier cancellation combiner has a substantially lower power carrier component than the output signal sampled by said second coupler.
26. A feed forward amplifier as set out in claim 25, wherein the output of said second carrier cancellation combiner has about 15\u201320 dB less power than the output signal sampled by said second coupler.
27. A method for amplifying an RF input signal employing feed forward compensation, comprising:
receiving an RF input signal and providing said signal on a main signal path;
sampling the RF input signal and providing the sampled RE input signal on a second signal path;
amplifying the signal on said main signal path employing a main amplifier;
sampling the main amplifier output;
delaying the sampled RF input signal on the second signal path;
coupling the delayed RF input signal to the sampled output from a main amplifier so as to cancel at least a portion of a carrier component of said sampled output from the main amplifier and provide a carrier canceled signal having a distortion component;
amplifying the carrier canceled signal employing an error amplifier to provide an error signal;
delaying the output of the main amplifier by a delay substantially less than the signal delay through the error amplifier;
combining the error signal and the delayed output of the main amplifier so as to cancel distortion introduced by the main amplifier and providing an amplified RF output;
sampling said amplified RF output;
combining the sampled amplified RF output with an anti-phase sample of the input signal to provide a carrier reduced sampled output;
down converting the carrier reduced sampled output using a variable frequency down converting signal; and
detecting out-of-band distortion using a digital signal processor to analyze the spectrum of the down converted signal.
28. A method as set out in claim 27, further comprising adjusting the gain and phase of the carrier canceled signal input to said error amplifier to minimize the detected out-of-band distortion.
29. A method as set out in claim 27, further comprising adjusting the gain and phase of at least one of the sampled amplified RF output and sampled input signal to reduce the carrier component of the down converted signal to a desired level.
30. A method as set out in claim 27, wherein the signal delay through the error amplifier is greater than the signal delay of the output of the main amplifier by at least 3 cycles of the RF input signal.
31. A method as set out in claim 27, wherein the signal delay through the error amplifier is about 10\u201320 ns. and the signal delay of the output of the main amplifier is less than about 3 ns.
32. A method as set out in claim 31, wherein the signal delay through the error amplifier is about 10 ns. and the signal delay of the output of the main amplifier is less than about 1.5 ns.
33. A method as set out, in claim 27, wherein the signal delay of the output of the main amplifier is less than about 30 percent of the signal delay through the error amplifier.
34. A method as set out in claim 27, wherein said RF input signal has a carrier bandwidth of about 5 MHz or less.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
a semiconductor chip having a plurality of electrodes on the surface thereof,
a plurality of lead terminal portions for external connection,
hanging lead portions coupled to a supporting portion on which the semiconductor chip is mounted,
metal wires for respectively connecting the lead terminal portions and the electrodes of the semiconductor chip to each other, and
a sealing resin for sealing the semiconductor chip and the metal wires in such a manner that a part of each lead terminal portion is exposed,
wherein lead terminal portions among the plurality of the lead terminal portions arranged adjacent to the hanging lead portions each have a chamfered portion at an end closer to the semiconductor chip, the chamfered portion is chamfered substantially along an adjacent one of the hanging lead portions, and four pairs of the chamfered portions are placed across the corresponding hanging lead portions,
wherein the plurality of lead terminal portions includes successively adjacent lead terminal portions each having a head side confronting the semiconductor chip, the head sides of the respective successively adjacent lead terminal portions being aligned along a straight line, and each of the head sides confronts a corresponding one of the head sides across the semiconductor chip, and
wherein the plurality of lead terminal portions are arranged in an area that is wider than the supporting portion in a side view.
2. The semiconductor device according to claim 1, wherein the chamfered lead terminal portions are each arranged to avoid interference with the adjacent one of the hanging lead portions.
3. The semiconductor device according to claim 1, wherein the chamfered portion extends substantially throughout a whole width of the lead terminal portion having the chamfered portion.
4. The semiconductor device according to claim 1, wherein an end face of the lead terminal portion is substantially in a same plane with a side surface of the sealing resin.
5. The semiconductor device according to claim 1, wherein a bottom surface of the lead terminal portion is exposed from a bottom surface of the sealing resin to form an outer lead portion.
6. The semiconductor device according to claim 1, wherein at least a part of a section of the lead terminal portion is in a shape of an inverted trapezoid.
7. The semiconductor device according to claim 1, wherein the chamfered portion includes a linear side that is parallel to a lateral side of the hanging lead portion and the linear side of the chamfered portion extends across substantially an entire width of the lead terminal portion having the chamfered portion.
8. The semiconductor device according to claim 1, wherein a side of the lead terminal portion includes a step.
9. The semiconductor device according to claim 1, wherein the hanging lead portions each have a step, whereby the supporting portion is offset from the lead terminal portions.
10. The semiconductor device according to claim 1, wherein the device has a cut-out corner portion.
11. The semiconductor device according to claim 10, wherein the cut-out corner portion has a side extending in a direction perpendicular to an adjacent one of the hanging lead portions.
12. The semiconductor device according to claim 10, wherein all corner portions of the device are the cut-out corner portions.
13. The semiconductor device according to claim 1, wherein the chamfered portion includes a curved side.
14. The semiconductor device according to claim 1, wherein the chamfered portion has an oblique side extending only in a part of the width of the chamfered lead terminal portion.
15. The semiconductor device according to claim 1, wherein the chamfered portion has an oblique side extending across substantially the entire width of the lead terminal portion having the chamfered portion.
16. The semiconductor device according to claim 1, wherein the device is substantially in a shape of a square and substantially symmetrical in two directions perpendicular to each other when viewed in plan.
17. The semiconductor device according to claim 1, wherein the hanging lead portions each extend diagonally from a corner of the device.
18. The semiconductor device according to claim 1, wherein the supporting portion is X-shaped.
19. The semiconductor device according to claim 1, wherein the supporting portion is larger in width than the hanging lead portion.
20. The semiconductor device according to claim 1, wherein the hanging lead portion is oblique with respect to a longitudinal direction of the lead terminal portions with an angle of approximately 45\xb0 in plan view.
21. The semiconductor device according to claim 1, wherein each of the lead terminal portions has a same length.
22. The semiconductor device according to claim 1, wherein each lead terminal portion not adjacent to the hanging lead portion has a head side formed perpendicular to a length thereof.
23. The semiconductor device according to claim 1, wherein the lead terminal portion has a tapered surface opposed to a bottom surface side of the sealing resin.
24. The semiconductor device according to claim 1, wherein the sealing resin is substantially in a same plane with a rear end of the lead terminal portion.
25. The semiconductor device according to claim 1, wherein an area of an upper surface of the supporting portion is smaller than an area of a bottom surface of the semiconductor chip.
26. The semiconductor device according to claim 1, wherein the sealing resin is present below the supporting portion by a thickness corresponding to a height of an upsetting of the supporting portion.
27. The semiconductor device according to claim 1, wherein a bottom of the semiconductor chip is in direct contact with the sealing resin.
28. The semiconductor device according to claim 1, wherein the hanging lead portion has a width different from a width of the supporting portion.
29. The semiconductor device according to claim 1, wherein at least a part of the lead terminal portion has a section having a lower side and an upper side longer than the lower side.
30. The semiconductor device according to claim 1, wherein bottom surfaces of the lead terminal portions and a bottom surface of the sealing resin are flush with each other.
31. The semiconductor device according to claim 1, wherein each of the lead terminal portions has a wide portion and a narrow portion.