We claim:
1. A fuse latch array system for storing fuse data for column redundancy applications for an embedded DRAM (eDRAM) system, the fuse latch array system comprising:
a plurality of fuse latch elements arranged in an array and having a plurality of bitlines traversing there through;
an data input line coupled to at least one of the plurality of fuse latch elements for inputting fuse data to the fuse latch array for storage therein;
a plurality of data connection lines each connecting adjacent fuse latch elements of the plurality of fuse latch elements for passage of fuse data there between; and
at least one clock signal line for inputting at least one clock signal to the fuse latch array for shifting fuse data within adjacent fuse latch elements via the plurality of data connection lines and within each of the plurality of fuse latch elements.
2. The system according to claim 1, further comprising:
a multiplexer circuit coupled to the plurality of fuse latch elements for accessing fuse data; and
a plurality of data output lines coupled to the multiplexer circuit for outputting the fuse data.
3. The system according to claim 1, further comprising buffers connecting a first group of fuse latch elements of the plurality of fuse latch elements with a second group of fuse latch elements of the plurality of fuse latch elements.
4. The system according to claim 3, wherein the first group of fuse latch elements are arranged in a first row of the array and the second group of fuse latch elements are arranged in a second row of the array.
5. The system according to claim 1, wherein fuse data is stored in the array sequentially starting from the at least one fuse latch element of the plurality of fuse latch elements which is coupled to the data input line.
6. The system according to claim 1, wherein each of the plurality of fuse latch elements includes a master latch and a slave latch coupled via a transmission gate.
7. The system according to claim 6, wherein, during a first clock period of a first clock signal of the at least one clock signal, fuse data are shifted to the master latches of each of the plurality of fuse latch elements, and, during a first clock period of a second clock signal of the at least one clock signal, fuse data are shifted to the slave latches of each of the plurality of fuse latch elements.
8. The system according to claim 7, wherein, during a second clock period of the first clock signal of the at least one clock signal, fuse data are shifted from the slave latches to the master latches of adjacent fuse latch elements of the plurality of fuse latch elements, and, during a second clock period of the second clock signal of the at least one clock signal, fuse data are shifted to the slave latches of each of the plurality of fuse latch elements.
9. The system according to claim 1, wherein fuse data corresponding to a bank of the eDRAM are read from the array by using a bank address corresponding to the bank.
10. The system according to claim 9, wherein the bank address includes a master fuse bit and a plurality of data bits for identifying a defective column location within the bank.
11. The system according to claim 9, wherein the master fuse bit and the plurality of data bits corresponding to the bank are stored within a group of fuse latch elements of the plurality of fuse latch elements, and wherein each of the group of fuse latch elements stores one of the master fuse bit and one of the plurality of data bits.
12. The system according to claim 1, wherein fuse data stored within a group of fuse latch elements corresponding to a bank of the eDRAM are simultaneously read from the group of fuse latch elements of the plurality of fuse latch elements.
13. The system according to claim 1, wherein fuse data stored within a group of fuse latch elements corresponding to a bank of the eDRAM are read via a page mode operation from the group of fuse latch elements of the plurality of fuse latch elements.
14. The system according to claim 1, wherein fuse data stored within a group of fuse latch elements corresponding to a bank of the eDRAM are read within one clock cycle from the group of fuse latch elements of the plurality of fuse latch elements.
15. The system according to claim 1, further comprising decoder circuitry for receiving a bank address corresponding to a bank of the eDRAM and decoding one of a plurality of wordlines traversing the array for locating at least one group of fuse latch elements of the plurality of fuse latch elements corresponding to the bank address and storing fuse data corresponding to the bank.
16. The system according to claim 15, further comprising means for checking a master fuse bit stored within the at least one group of fuse latch elements and determining if a dataline replacement operation is necessary.
17. The system according to claim 16, wherein the dataline replacement operation is necessary if the master fuse bit has logic high state.
18. The system according to claim 16, further comprising at least one decoder for receiving fuse latch bits stored within the at least one group of fuse latch elements and outputting a set of signals for activating at least one of a plurality of switches of a multiplexer circuit if the dataline replacement operation is necessary.
19. The system according to claim 1, wherein the plurality of fuse latch elements are located in proximity to banks of the eDRAM.
20. The system according to claim 1, further comprising a data path originating at the data input line and sequentially connecting the plurality of fuse latch elements.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-31. (canceled)
32. A memory device, comprising:
an address bus;
a control bus;
an internal data bus;
an address decoder coupled to the address bus;
a control circuit coupled to the control bus;
a memory-cell array coupled to the address decoder, control circuit; and
a readwrite circuit coupled to the memory-cell array through the internal data bus to output data received from the memory-cell array, the readwrite circuit including a synchronous data output circuit, comprising:
an output driver having a data input terminal coupled to the internal data bus to receive input data, an output terminal at which output data is provided, and a clock terminal at which a clock signal is applied, the output driver operable to provide the input data as the output data in response to the clock signal;
a synchronizing circuit having an input terminal at which an external clock signal is applied and having an output terminal at which an internal clock signal is provided; and
a delay circuit having an input coupled to the output of the synchronizing circuit, an output coupled to the clock terminal of the output driver, and a selection terminal for receiving a selection signal, the delay circuit operable to provide the clock signal to synchronize output by the output driver having a delay with respect to the internal clock signal according to one of a plurality of programmable time delays selected in accordance with the selection signal.
33. The memory device of claim 32 wherein the synchronous data output circuit further comprises a data strobe signal generator coupled to the output driver to generate a data strobe signal, the output driver further operable to output the data strobe signal in response to the clock signal applied to the clock terminal.
34. The memory device of claim 32 wherein the synchronizing circuit of the synchronous data output circuit comprises a delay-locked loop (DLL).
35. The memory device of claim 34 wherein the DLL comprises a DLL having a delay component that varies proportionately as a function of input clock frequency.
36. The memory device of claim 35 wherein the plurality of delay circuits comprise at least first and second delay circuits having first and second time delays, respectively, the first time delay greater than the second time delay, the first delay circuit activated for an input clock frequency less than a threshold frequency and the second delay circuit activated for an input clock frequency greater than the threshold frequency.
37. The memory device of claim 32 wherein each of the plurality of delay circuits comprises a programmable delay element.
38. The memory device of claim 37 wherein each of the programmable delay elements comprise a delay element programmable by programming antifuses.
39. The memory device of claim 32 wherein the plurality of delay circuits are further coupled to receive as the selection signal a signal indicative of a CAS latency value.
40. The memory device of claim 39 wherein the plurality of delay circuits comprise a number of delay circuits equal to the number of potential CAS latency values.
41-54. (canceled)