1. A precision sampling circuit, comprising:
a plurality of inputs, each input having a data line and a data complement line, a signal on each input includes a transition on the data input line and a transition on the data complement, wherein the transition on the data line begins at substantially a same time as the transition on the data complement line, and the transition on the data line includes substantially a same duration as and the transition on the data complement line;
a plurality of output lines;
a plurality of flip-flops, each flip-flop connected to one of the plurality of input lines, wherein the data line is connected to a flip-flop data input line and the data complement line is connected to a flip-flop data complement input line, wherein each flip-flop includes an output line connected to one of the plurality of output lines; and
a clock line connected to each of the plurality of flip-flops.
2. The precision sampling circuit of claim 1, wherein for each flip-flop, the flip-flop further comprises:
a first differential pair transistor connected directly to the flip-flop data input line; and
a second differential pair transistor connected directly to the flip-flop data complement input line.
3. The precision sampling circuit of claim 2, wherein a clock signal on the clock line is operable to trigger each flip-flop to sample the plurality of inputs.
4. The precision sampling circuit of claim 2, wherein for each flip-flop, the flip-flop further comprises:
a first pre-charge node connected to the first differential pair transistor; and
a second pre-charge node connected to the second differential pair transistor.
5. The precision sampling circuit of claim 2, wherein for each flip-flop, the flip-flop is operable to capture a logical value present on the flip-flop data input line and flip-flop data complement line by a discharge of one of the first and second pre-charge nodes through a path to ground through one of the first and second differential pair transistors, the path to ground being created by a logical high value on one of the flip-flop data input line and flip-flop data complement lines.
6. The precision sampling circuit of claim 2, wherein the first and second differential pair transistor switch during approximately the same time interval.
7. The precision sampling circuit of claim 1, further comprising:
a delay circuit on the clock line, wherein the delay circuit is operable to delay the clock signal for a predetermined time following the clock signal being received at a clock line input.
8. A method of sampling a plurality of inputs, comprising:
for each of the plurality of inputs, receiving a data input signal and a data complement input signal, wherein the data input and the data complement input are substantially symmetrical and substantially simultaneous;
providing the data input signal directly to a first differential pair transistor;
providing the data complement signal directly to a second differential pair transistor; and
selectively discharging one of a first and second node based on a switching of one of the differential pair transistors.
9. The method of claim 8, wherein the first and second nodes are pre-charge nodes that are each charged to a high voltage during a failing edge of a clock signal.
10. The method of claim 9, wherein selectively discharging one of the first and second nodes includes discharging through one of the differential pair transistors through a path to ground that includes an evaluate transistor.
11. The method of claim 10, wherein the evaluate transistor is turned on by a rising edge of the clock signal.
12. The method of claim 8, wherein the first and second differential pair transistor switch during approximately the same time interval.
13. The method of claim 9, further comprising:
receiving an input clock signal;
delaying the input clock signal for a predetermined time to form the clock; and
providing the clock signal to selectively discharge on the one of the first and second nodes.
14. The method of claim 13, wherein the input clock signal is additionally used to trigger a wavefront in a delay chain and the predetermined time is chosen such that the one of a first and second nodes is selectively discharged before the wavefront reaches an end of the delay chain.
15. A method of sampling a differential input, comprising:
receiving a data input signal and a data complement input signal, wherein the data input and the data complement input are substantially symmetrical and substantially simultaneous;
providing the data input signal directly to a first differential pair transistor;
providing the data complement signal directly to a second differential pair transistor; and
selectively discharging one of a first and second node based on a switching of one of the differential pair transistors.
16. The method of claim 15, wherein the first and second nodes are pre-charge nodes that are each charged to a high voltage during a falling edge of a clock signal.
17. The method of claim 16, wherein selectively discharging one of the first and second nodes includes discharging through one of the differential pair transistors through a path to ground that includes an evaluate transistor.
18. The method of claim 17, wherein the evaluate transistor is turned on by a rising edge of the clock signal.
19. The method of claim 15, wherein the first and second differential pair transistor switch during approximately the same time interval.
20. The method of claim 16, further comprising:
receiving an input clock signal;
delaying the input clock signal for a predetermined time to form the clock signal; and
providing the clock signal to selectively discharge on the one of the first and second nodes.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A device for simultaneously displaying the time in at least a first time zone and a second time zone, the device comprising:
a plurality of clocks mounted on the device, the plurality of clocks comprising at least a first clock and a second clock; and
a map of a geographical area mounted on the device, the map depicting a plurality of time zones, the plurality of time zones comprising at least the first time zone and the second time zone;
wherein the first clock is positioned proximate to the first time zone and the second clock is positioned proximate to the second time zone.
2. The device of claim 1, wherein the first clock is positioned on the device directly above the first time zone and the second clock is positioned on the device directly above the second time zone.
3. The device of claim 1, wherein the first clock is positioned on the device directly below the first time zone and the second clock is positioned on the device directly below the second time zone.
4. The device of claim 1, wherein the geographical area comprises the continental 48 states of the United States of America;
the plurality of clocks mounted on the device further comprises at least a third clock and a fourth clock;
the plurality of time zones further comprises at least a third time zone and a fourth time zone; and
the first time zone is the Pacific time zone, the second time zone is the Mountain time zone, the third time zone is the Central time zone, and the fourth time zone is the Eastern time zone.
5. The device of claim 1, wherein the first clock is mounted to the device within a first clock mounting area of the device and the second clock is mounted to the device within a second clock mounting area of the device and the first time zone and the first clock mounting area are marked with a first discernible identifier and the second time zone and second clock mounting area are marked with a second discernible identifier differing from the first discernible identifier.
6. The device of claim 1, wherein the first clock is mounted to the device within a first clock mounting area of the device and the second clock is mounted to the device within a second clock mounting area of the device and the first time zone and the first clock are marked with a first discernible identifier and the second time zone and second clock are marked with a second discernible identifier differing from the first discernible identifier.
7. The device of claims 5 or 6, wherein the first and second discernible identifiers are selected from the group consisting of: shades, colors, and alphanumeric characters.
8. The device of claim 1, wherein the device comprises a front portion comprising the plurality of clocks and the map of the geographical area; and a back portion comprising a fastener for affixing the device to the dashboard of a motor vehicle.
9. The device of claim 8, wherein the fastener is selected from the group consisting of an adhesive, a mechanical connector, and a hook and loop type connector.
10. The device of claim 1, wherein the device comprises a front portion comprising the plurality of clocks and the map of the geographical area; a back portion; and a base portion for supporting the device on a horizontal surface.
11. The device of claim 10, wherein the base portion comprises a non-slip material.
12. The device of claim 10, wherein the front portion is substantially planar.
13. The device of claim 10, wherein the front portion is non-planar.
14. The device of claim 1, wherein at least one of the plurality of clocks is an analog clock.
15. The device of claim 1, wherein at least one of the plurality of clocks is a digital clock.
16. The device of claim 1, wherein at least one of the plurality of clocks is a battery-operated clock.
17. The device of claim 1, wherein at least one of the plurality of clocks is reversibly mounted to the device.
18. A device for simultaneously displaying the time in at least a first time zone, a second time zone, a third time zone, and a fourth time zone, the device comprising:
a plurality of clocks mounted on the device, the plurality of clocks comprising at least a first clock, a second clock, a third clock and a fourth clock; and
a map comprising the continental 48 states of the United States of America mounted on the device, the map depicting a plurality of time zones, the plurality of time zones comprising at least the first time zone, the second time zone, the third time zone, and the fourth time zone;
wherein the first clock is positioned proximate to the first time zone, the second clock is positioned proximate to the second time zone, the third clock is positioned proximate to the third time zone, and the fourth clock is positioned proximate to the fourth time zone, and
wherein the first time zone is the Pacific time zone, the second time zone is the Mountain time zone, the third time zone is the Central time zone, and the fourth time zone is the Eastern time zone.
19. The device of claim 18, wherein the first clock is mounted to the device within a first clock mounting area of the device and the second clock is mounted to the device within a second clock mounting area of the device and the first time zone and the first clock mounting area are marked with a first discernible identifier and the second time zone and second clock mounting area are marked with a second discernible identifier differing from the first discernible identifier.
20. A method for determining the time in a different time zone, the method comprising the steps of:
(a) providing a device in a first time zone, the device comprising a plurality of clocks mounted on the device, the plurality of clocks comprising at least a first clock and a second clock; and a map of a geographical area mounted on the device, the map depicting a plurality of time zones, the plurality of time zones comprising at least the first time zone and a second time zone, wherein the first clock is positioned proximate to the first time zone and the second clock is positioned proximate to the second time zone; and
(b) determining the time on the second clock.