1. A semiconductor device, comprising:
a semiconductor body including a surface and an opposing surface, said semiconductor body comprising a first power electrode on said surface of said semiconductor body, and a second power electrode on said opposing surface of said semiconductor body;
a first barrier layer over a surface of said first power electrode;
a second barrier layer over a surface of said second power electrode;
a first metallic body having a resistivity less than the resistivity of said first electrode formed over said first barrier layer, wherein said first barrier prevents the contamination of said first electrode by said first metallic body; and
a second metallic body having a resistivity less than the resistivity of said second electrode formed over said second barrier layer, wherein said second barrier prevents the contamination of said second electrode by said second metallic body;
wherein said first metallic body has an increased thickness providing a substantially reduced resistivity and said first barrier layer is substantially thinner than said first metallic body;
wherein said first metallic body and said second metallic body are configured for flip-chip-type mounting and said first barrier layer and said second barrier layer comprise the same material.
2. The device of claim 1, wherein said first and second electrodes are comprised of one of aluminum, AlSi, and AlSiCu.
3. The device of claim 1, wherein said barrier layers are comprised of titanium.
4. The device of claim 1, wherein said first and said second metallic bodies are comprised of copper.
5. The device of claim 4, further comprising a nickel layer over at least one of said metallic bodies to balance the stress on said semiconductor device.
6. The device of claim 1, further comprising a metallic stress balancing body disposed on at least one of said metallic bodies.
7. The device of claim 6, wherein said metallic stress balancing body is comprised of nickel.
8. The device of claim 1, wherein said semiconductor device includes a semiconductor body that is 100 microns or less thick.
9. The device of claim 1, wherein said semiconductor device is a power MOSFET, and said first and said second electrodes are the source electrode and the drain electrode.
10. The device of claim 1, wherein said semiconductor device further comprises a control electrode, a third barrier layer over a surface of said control electrode, and a third metallic body having a resistivity less than the resistivity of said control electrode formed over said third barrier layer.
11. The device of claim 1, further comprising a solderable body over said first metallic body and a solderable body over said second metallic body.
12. The device of claim 11, wherein said solderable body is comprised of a nickel layer over said copper body and a lead tin layer over said nickel layer.
13. The device of claim 11, wherein each solderable body is comprised of either NiAg or NiAu.
14. A semiconductor device, comprising:
a semiconductor body including a surface and an opposing surface, said semiconductor body comprising a first power electrode on said surface of said semiconductor body, and a second power electrode on said opposing surface of said semiconductor body;
a first barrier layer over a surface of said first power electrode;
a second barrier layer over a surface of said second power electrode;
a first metallic body having a resistivity less than the resistivity of said first electrode formed over said first barrier layer, wherein said first barrier layer prevents the diffusion of metal from said first metallic body into said first power electrode;
wherein said first metallic body has an increased thickness providing a substantially reduced resistivity and said first barrier layer is substantially thinner than said first metallic body;
wherein said first metallic body is configured for flip-chip-type mounting and said first barrier layer and said second barrier layer comprise the same material.
15. The device of claim 14, further comprising a metallic stress balancing body comprised of nickel disposed on said first metallic body.
16. The device of claim 15, wherein said first metallic body comprises copper.
17. The device of claim 16, wherein said barrier layers are comprised of titanium.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A flash memory device comprising:
a local bit line connected to a bit line on a semiconductor substrate having a first conductive type;
a local source line connected to a common source line intersecting the bit line; and
a plurality of memory cells connected in parallel to the local bit line and the local source line,
wherein the local bit line and the local source line are vertically spaced apart from each other in the semiconductor substrate to define respective vertical channels and comprise a first doped layer and a second doped layer, respectively, the first and second doping layers having a second conductive type.
2. The device of claim 1, further comprising:
a first select transistor connecting the bit line with the local bit line;
a second select transistor connecting the common source line with the local source line;
a drain select line and a source select line connected to the first select transistor and the second select transistor, respectively, and arranged to intersect the bit line; and
a plurality of word lines connected to the memory cells to intersect the bit line, between the drain select line and the source select line.
3. The device of claim 2, further comprising a semiconductor pin protruding from the semiconductor substrate to extend in one direction and having the top surface and the side surface,
wherein the doped layers of the local bit line and the local source line extend along the direction in an upper portion or a lower portion of the semiconductor pin,
wherein the word lines, the drain select line, and the source select line extend over the top surface and the side surface of the semiconductor pin to intersect the direction.
4. The device of claim 3, further comprising a tunnel insulating layer, a charge storage layer, and a blocking insulating layer between the word lines and the semiconductor pin.
5. The device of claim 3, further comprising an isolation insulating layer provided between the lower portion of the semiconductor pin and lower portions of other semiconductor pins adjacent to the semiconductor pin to extend along the direction,
wherein the word lines, the drain select line, and the source select line extend over the isolation insulating layer.
6. The device of claim 3, wherein the first doped layer is provided in the upper portion of the semiconductor pin, and the second doped layer is provided in the lower portion of the semiconductor pin;
the device further comprising a third doped layer and a fourth doped layer spaced apart from each other at both sides of the first doped layer in the upper portion of the semiconductor pin, the third and fourth doped layers having a second conductive type,
wherein the word lines overlap the first doped layer and the second doped layer, the source select line overlaps the second doped layer and the third doped layer, and the drain select line is provided between the first doped layer and the fourth doped layer.
7. The device of claim 6, further comprising a body isolation line extending over the top surface and the side surface of the semiconductor pin to intersect the direction and overlapping the first doped layer and the second doped layer to deplete a body region between the first doped layer and the second doped layer, between the drain select line and the word line that is the most adjacent to the drain select line.
8. The device of claim 3, wherein the first doped layer is provided in the upper portion of the semiconductor pin, and the second doped layer is provided in the lower portion of the semiconductor pin;
the device further comprising a third doped layer spaced apart from the first doped layer and having a second conductive type in the upper portion of the semiconductor pin, and a fourth doped layer spaced apart from the second doped layer and having a second conductive type in the lower portion of the semiconductor pin,
wherein the word lines overlap the first doped layer and the second doped layer, the source select line overlaps the second doped layer and the third doped layer, and the drain select line overlaps the first doped layer and the fourth doped layer.
9. The device of claim 3, wherein the first doped layer is provided in the upper portion of the semiconductor pin, and the second doped layer is provided in the lower portion of the semiconductor pin
the device further comprising a fourth doped layer spaced apart from the first doped layer and having a second conductive type in the upper portion, and a third doped layer spaced apart from the second doped layer and having a second conductive type in the lower portion of the semiconductor pin,
wherein the word lines overlap the first doped layer and the second doped layer, the source select line is provided between the second doped layer and the third doped layer, and the drain select line is provided between the first doped layer and the fourth doped layer.
10. The device of claim 3, wherein the first doped layer is provided in the upper portion of the semiconductor pin, and the second doped layer is provided in the lower portion of the semiconductor pin; and
the semiconductor substrate includes a buried insulating layer, the buried insulating layer being provided in the lower portion of the semiconductor pin to electrically insulate the semiconductor pin from other semiconductor pins adjacent to the semiconductor pin, and contacting a bottom surface of the second doped layer.
11. The device of claim 10, further comprising:
a third doped layer and a fourth doped layer spaced apart in the both sides of the first doped layer in the upper portion of the semiconductor pin; and
a fifth doped layer spaced apart from the second doped layer and contacting the top surface of the buried insulting layer in the lower portion of the semiconductor pin,
wherein the word lines overlap the first doped layer and the second doped layer, the source select line overlaps the second doped layer and the third doped layer, and the drain select line is provided between the first doped layer and the fourth doped layer and overlaps the fifth doped layer.
12. The device of claim 3, wherein the first doped layer is provided in the lower portion of the semiconductor pin, and the second doped layer is provided in the upper portion of the semiconductor pin;
the device further comprising a fourth doped layer spaced apart from the second doped layer and having a second conductive type in the upper portion of the semiconductor pin, and a fifth doped layer extending from the third doped layer toward the top surface of the semiconductor pin and having a second conductive type;
wherein the word lines overlap the first doped layer and the second doped layer, the source select line overlaps the second doped layer and the third doped layer, and the drain select line overlaps the first doped layer and the fourth doped layer.
13. The device of claim 12, further comprising:
a body isolation line extending over the top surface and the side surface of the semiconductor pin to intersect the direction and overlapping the first doped layer and the second doped layer to deplete a body region between the first doped layer and the second doped layer, between the source select line and the word line that is the most adjacent to the source select line.
14. The device of claim 3, wherein the width of the semiconductor pin ranges from about 40 nm to about 60 nm.
15. A flash memory device comprising:
a semiconductor pin protruding from a semiconductor substrate of a first conductive type to extending in a direction and including a top surface and a side surface;
a first doped layer and a second doped layer provided in an upper portion and a lower portion of the semiconductor pin, respectively, to be vertically spaced apart from each other, the first and second doped layers having a second conductive type; and
a plurality of word lines extending over the top surface and the side surface of the semiconductor pin to intersect the direction and interposing a tunnel insulating layer, a charge storage layer, and a blocking insulating layer between the semiconductor pin and the plurality of word lines,
wherein the word lines overlap the first doped layer and the second doped layer to have vertical channels.
16. The device of claim 15, further comprising:
a source select line and a drain select line extending to intersect the direction at the both sides of the word lines;
a common source line connected to the semiconductor pin at one side of the source select line opposite to the word lines; and
a bit line connected to the semiconductor pin at the other side of the drain select line opposite to the word lines,
wherein the first doped layer and the second doped layer are a local bit line or a local source line, respectively, the local bit line connecting in parallel memory cells connected to the word lines with the bit line, the local source line connecting in parallel the memory cells with the common source line, the device constituting an AND flash memory.
17. The device of claim 16, further comprising:
a body isolation line extending over the top surface and the side surface of the semiconductor pin to intersect the direction and overlapping the first doped layer and the second doped layer to deplete a body region between the first doped layer and the second doped layer, between the outmost word line and the select line adjacent to the outmost word line.
18. The device of claim 15, wherein the first doped layer and the second doped layer are a bit line and a common source line, respectively, the device constituting a NOR flash memory.
19. A method of operating an AND flash memory device, the AND flash memory device including a plurality of bit lines, a local bit line connected to each of the bit lines through a first select transistor controlled by a drain select line, common source lines, a local source line connected to each of the commons source lines through a second select transistor controlled by a source select line, and a plurality of memory cells connected in parallel to the local bit line and the local source line and controlled by word lines on a semiconductor substrate, the method comprising:
by applying a first voltage to the drain select line, a second voltage lower than the first voltage to the bit line connected to selected memory cell to turn on the first select transistor, a third voltage equal to or higher than the first voltage to the bit lines connected to unselected memory cells, a fourth voltage higher than the second voltage to the word line connected to the selected memory cell, a fifth voltage equal to or higher than the second voltage or lower than the fourth voltage to the word lines connected to the unselected memory cells, the second voltage to the source select line to turn off the second select transistor, the second voltage to the common source line, and a ground voltage to the semiconductor substrate,
floating a body region of the selected memory cell from electric potential of the semiconductor substrate to program the selected memory cell.
20. The method of claim 19, wherein the AND flash memory device comprises the structure of claim 13, and a sixth voltage is applied to the body isolation line to completely deplete a body region of a semiconductor pin surrounded by the body isolation line.
21. The method of claim 20, further comprising, by applying a seventh voltage to word lines of memory cells in a specific block including the selected memory cell and disposed between the drain select line and the source select line not to completely deplete a body region of the memory cells in the specific block and an eighth voltage higher than the seventh voltage to the semiconductor substrate to move electron hoes through F-N tunneling in the body region of the memory cells in the specific block, and floating the remaining lines,
simultaneously erasing the memory cells in the specific block.
22. The method of claim 21, further comprising, by applying a ninth voltage to the body isolation line not to completely deplete the body region of the semiconductor pin surrounded by the body isolation line, a tenth voltage higher than a ground voltage to the source select line to turn on the second select transistor, an eleventh voltage higher than the ground voltage to a word line connected to the selected memory cell, the first voltage higher than the ground voltage to the drain select line to turn on the first select transistor, a twelfth voltage higher than the ground voltage to a bit line connected to the selected memory cell, and the ground voltage to the common source line, word lines connected to the unselected memory cell, unselected bit lines, and the semiconductor substrate,
reading the selected memory cell.
23. The method of claim 22, wherein the fifth voltage and the ninth voltage are the ground voltage.
24. The method of operating the device of claim 19, further comprising, by applying a program voltage to a word line of selected memory cell, a floating or ground voltage to word lines of unselected memory cells and unselected bit lines, a first write voltage higher than the ground voltage to a bit line connected to the selected memory cell, and the ground voltage to the common source line,
programming the charge storage layer on the drain of the selected memory cell through a channel hot electron injection method.
25. The method of claim 24, further comprising, by applying a program voltage to a word line of selected memory cell, a floating or ground voltage to word lines of unselected memory cells and unselected bit lines, the ground voltage is applied to a bit line connected to the selected memory cell, and a second write voltage higher than the ground voltage to the common source line,
programming the charge storage layer on the source of the selected memory cell through a channel hot electron injection method.
26. The method of claim 25, wherein the common source line of the semiconductor pin and the common source line of other semiconductor pins are electrically insulated from each other, and a body region of the semiconductor pin and body regions of other semiconductor pins are independently biased.
27. A flash memory device comprising:
doped local bit lines in a substrate having non-volatile memory cells thereon; and
doped local source lines in the substrate buried under the doped local bit lines to be vertically spaced apart from one another and to define vertical channels for the respective non-volatile memory cells wherein a portion of layers forming the doped local bit lines and the doped local source lines are vertically non-overlapping.