1. A computer-implemented method, comprising:
forward transforming a set of co-located blocks corresponding to plural matched frames, wherein forward transforming the co-located blocks comprises determining a step size for processing pixels within the matched frames, the step size being correlated with a quantity of the pixels in each block of the matched frames, wherein the plural matched frames are determined by frame matching, and wherein frame matching comprises collapsing a predetermined number of frames into a summations frame FSUM, wherein FSUM
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computing a difference measure for a subset of coefficients between a set of transformed blocks and a reference block, the computation in a two-dimensional (2D) transform domain; and
selectively thresholding, in accordance with a temporal mode, one or more of the co-located transformed blocks based on the number of transformed blocks having a difference measure below a predetermined threshold.
2. The method of claim 1, wherein forward transforming comprises 2D transforming.
3. The method of claim 1, wherein the subset of coefficients corresponds to the lower frequency components of the 2D transform, zig-zag scanned to one-dimension (1D).
4. The method of claim 1, wherein the subset of coefficients corresponds to a defined quantity of the lowest frequency elements of the transformed blocks.
5. The method of claim 1, wherein the subset of coefficients corresponds to a subset of the coefficients of the 2D transformed blocks.
6. The method of claim 1, further comprising communicating the difference measure for the subset of coefficients of the transformed blocks for determination of the temporal mode, the determination based on a comparison of the subset with a predefined threshold subband difference measure value, the temporal mode used to determine which of the co-located transformed blocks to threshold.
7. The method of claim 1, wherein computing comprises rejecting noise not belonging to the subset.
8. The method of claim 1, wherein selectively thresholding consists of three-dimensional (3D) thresholding co-located blocks temporally subsequent to a matched reference frame of the matched frames.
9. The method of claim 1, wherein selectively thresholding consists of three-dimensional (3D) thresholding co-located blocks temporally previous to a matched reference frame of the matched frames.
10. The method of claim 1, wherein selectively thresholding consists of 2D thresholding the co-located block of a matched reference frame of the matched frames.
11. The method of claim 1, wherein selectively thresholding consists of three-dimensional dimensional (3D) thresholding co-located blocks corresponding to all of the matched frames.
12. A system, comprising:
transform logic configured to:
forward transform a set of co-located blocks corresponding to plural matched frames, wherein forward transforming the co-located blocks comprises determining a step size for processing pixels within the matched frames, the step size being correlated with a quantity of the pixels in each block of the matched frames, wherein the plural matched frames are determined by frame matching, and wherein frame matching comprises collapsing a predetermined number of frames into a summations frame FSUM, wherein FSUM
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compute a difference measure in a transform domain for a subset of coefficients corresponding to the transformed blocks, the computation being associated with the rejection of noise; and
threshold logic configured to selectively threshold, in accordance with a temporal mode, one or more of the co-located blocks based on the number of transformed blocks having a computed difference measure values below a predetermined threshold.
13. The system of claim 12, wherein the transform logic is configured to implement two-dimensional (2D) transforming.
14. The system of claim 12, wherein the subset of coefficients corresponds to a defined quantity of the lowest frequency elements of two-dimensional (2D) transformed blocks, the lowest frequency elements ordered by zig-zag scanning the 2D transformed blocks to one-dimension (1D).
15. The system of claim 12, further comprising temporal mode logic configured to receive the difference measure for the subset from the transform logic and determine the temporal mode, the determination based on a comparison of the subset with a predefined threshold subband difference measure value, the temporal mode used to determine which of the co-located transformed blocks to threshold.
16. The system of claim 15, wherein the threshold logic is configured to selectively threshold by three-dimensional (3D) thresholding, exclusively, co-located 3D transformed matched blocks temporally subsequent to a matched reference frame of the matched frames, the thresholding responsive to signalling from the temporal mode logic.
17. The system of claim 15, wherein the threshold logic is configured to selectively threshold by three-dimensional (3D) thresholding, exclusively, co-located 3D transformed matched blocks temporally previous to a matched reference frame of the matched frames, the thresholding responsive to signalling from the temporal mode logic.
18. The system of claim 15, wherein the threshold logic is configured to selectively threshold by two-dimensional (2D) thresholding, exclusively, a block of a matched reference frame of the matched frames, the thresholding responsive to signalling from the temporal mode logic.
19. The system of claim 15, wherein the threshold logic is further configured to selectively threshold by three-dimensional (3D) thresholding co-located 3D transformed matched blocks corresponding to all of the matched frames, the thresholding responsive to signalling from the temporal mode logic.
20. A computer-implemented method, comprising:
computing a difference measure for a set of coefficients of a two-dimensional (2D) transformed set of co-located matched blocks corresponding to plural matched frames blocks, the computation implemented in a 2D transform domain, a pixel size of each block of the co-located blocks being determined by a step-size used in processing pixels in the matched frames blocks, wherein the plural matched frames are determined by frame matching, and wherein frame matching comprises collapsing a predetermined number of frames into a summations frame FSUM, wherein FSUM
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and
selectively thresholding, in accordance with a temporal mode, one or more of the co-located 2D or three-dimensional (3D) transformed matched blocks based on the computed subband difference measure in comparison to a defined subband difference measure threshold value and based on the number of transformed blocks having a subband difference measure value below a predetermined threshold.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A clock pattern generating method of a semiconductor memory device, comprising:
generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state; and
generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.
2. The clock pattern generating method of claim 1, wherein in the second state, first clock patterns are output via a first group of the detection clock output pins, and second clock patterns are output via a second group of the detection clock output pins.
3. The clock pattern generating method of claim 2, wherein the first clock patterns include pseudo random binary pattern signals.
4. The clock pattern generating method of claim 3, wherein the pseudo random binary pattern signals have the same phase or have phases different from each other.
5. The clock pattern generating method of claim 2, wherein the second clock patterns include pseudo random binary pattern signals.
6. The clock pattern generating method of claim 5, wherein the pseudo random binary pattern signals have the same phase or have phases different from each other.
7. The clock pattern generating method of claim 1, wherein the plurality of detection clock output pins are error detection code pins.
8. The clock pattern generating method of claim 1, wherein the clock patterns different from each other are error detection code hold patterns.
9. The clock pattern generating method of claim 8, wherein the error detection code hold patterns are output via the error detection code pins for a clock data recovery function of a graphics processing unit.
10. The clock pattern generating method of claim 1, wherein the clock pattern is an error detection signal to detect an error state of data transmitted or received.
11. A semiconductor memory device, comprising:
a plurality of detection clock output pins; and
a clock pattern generating unit configured to generate the same clock pattern through the plurality of detection clock output pins when an output selection control signal is in a first state and clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.
12. The semiconductor memory device of claim 11, wherein in the second state, the clock pattern generating unit is configured to output first clock patterns via a first group of the detection clock output pins and is configured to output second clock patterns via a second group of the detection clock output pins.
13. The semiconductor memory device of claim 11, wherein when the second clock patterns include pseudo random binary pattern signals, the second clock patterns have the same phase or have phases different from each other.
14. The semiconductor memory device of claim 11, wherein the output selection control signal includes a mode register set signal.
15. The semiconductor memory device of claim 11, wherein the semiconductor memory device is disposed on a memory module.
16. A semiconductor memory device, comprising:
a plurality of detection clock output pins, wherein the plurality of detection clock output pins include a first group of the detection clock output pins and a second group of the detection clock output pins,
a clock pattern generating unit configured to generate a first pair of clock patterns through the first group of the detection clock output pins and a second pair of clock patterns through the second group of the detection clock output pins, wherein the first pair of clock patterns have a different waveform from a waveform of the second pair of clock patterns.
17. The semiconductor memory device of claim 16, wherein the first pair of clock patterns include the same phase as each other, and the second pair of clock patterns include the same phase as each other.
18. The semiconductor memory device of claim 16, wherein the first pair of clock patterns include different phases from each other, and the second pair of clock patterns include different phases from each other.
19. The semiconductor memory device of claim 16, wherein the first pair of clock patterns include differential signals, and the second pair of clock patterns include different signals.
20. The semiconductor memory device of claim 16, wherein waveforms of the first and second pairs of clock patterns are controlled by an output selection control signal.