1. An operating method of a storage device which includes a nonvolatile memory including a plurality of memory cells; and a memory controller adapted to control the nonvolatile memory, the operating method comprising:
receiving write data to be written at the plurality of memory cells;
generating a determination by determining whether the received write data is least significant bit (LSB) data to be written at the plurality of memory cells; and
encoding the write data according to the determination,
wherein the write data is encoded according to the write data when the write data is LSB data to be written at the plurality of memory cells, and
wherein the write data is encoded according to the write data and encoding data of lower data of the write data to be written at the plurality of memory cells when the write data is not LSB data to be written at the plurality of memory cells.
2. The operating method of claim 1, wherein LSB data, central significant bit (CSB) data and most significant bit (MSB) data are written at each of the plurality of memory cells,
wherein data that is written as LSBs of data to be written at the plurality of memory cells and is first received is the LSB data,
wherein data that is written as CSBs of data to be written at the plurality of memory cells and is received following the LSB data is the CSB data,
wherein data that is written as MSBs of data to be written at the plurality of memory cells and is received following the CSB data is the MSB data, and
wherein the CSB data is lower data of the MSB data, and the LSB data is lower data of the MSB data and CSB data.
3. The operating method of claim 1, wherein each of the plurality of memory cells has one of at least first to eighth threshold voltage states according to LSB data, central significant bit (CSB) data, and most significant bit (MSB) data, and
wherein when the write data is the LSB data, the encoding the write data according to the determination includes decoding the LSB data such that a number of bits in the write data corresponding to an LSB value that is the same as an LSB value of a highest threshold voltage state is reduced, the highest threshold voltage state being a highest one of the at least first to eighth threshold voltage states.
4. The operating method of claim 3, wherein when the write data is the CSB data,
the operating method further comprises:
detecting bits, from among the encoded LSB data, having a same value as the LSB value of the highest threshold voltage states, and
the encoding the write data according to the determination includes encoding the CSB data is such that, with respect to first data, a number of bits in the first data corresponding to a CSB value that is the same as a CSB value of the highest threshold voltage state, is reduced,
the first data being data, from among the write data, for which values of the encoded LSB data are the same as the LSB value of the highest threshold voltage state.
5. The operating method of claim 4, wherein when the write data is the MSB data,
the operating method further comprises:
detecting bits, from among the encoded LSB data, having a same value as the LSB value of the highest threshold voltage states,
detecting bits, from among the encoded CSB data, having a same value as the CSB value of the highest threshold voltage states, and
the encoding the write data according to the determination includes encoding the MSB data such that, with respect to second data, a number of bits in the second data corresponding to a MSB value that is the same as a MSB value of the highest threshold voltage state, is reduced,
the second data being data, from among the write data, for which values of the encoded LSB data are the same as the LSB value of the highest threshold voltage state and values of the encoded CSB data are the same as the CSB value of the highest threshold voltage state.
6. The operating method of claim 1, wherein the encoding the write data according to the determination includes encoding the write data such that,
a value of a first portion of the write data is changed according to either,
the write data, or
a combination of the write data and encoding data of the lower data, and
a value of a second portion of the write data is changed according to the write data regardless of the encoding data of the lower data.
7. The operating method of claim 1, wherein the encoding the write data according to the determination includes encoding the write data such that the write data is encoded according to encoding data of second data to be written at second memory cells adjacent to the plurality of memory cells.
8. The operating method of claim 7, further comprising:
writing the encoded write data such that at least an LSB, a CSB, and an MSB are written at each of the plurality of memory cells and each of the second memory cells,
wherein each of the plurality of memory cells and each of the second memory cells has one of the at least first to at least eight threshold voltage states, the at least first to at least eighth threshold voltage states each corresponding to values for an LSB, a CSB, and an MSB,
wherein locations of bits, corresponding to a highest threshold voltage state, from among at least first through eighth threshold voltage states, are detected from the encoding data of the second data, and
wherein the write data is encoded such that data corresponding to a lowest threshold voltage, from among the at the least first through eighth threshold voltage states, are not written in memory cells at the detected locations.
9. The operating method of claim 1, wherein the write data is first write data and the method further comprises:
receiving first data; and
dividing the first data into the first write data, second write data, and third write data,
wherein the first write data is selected as the LSB data to be written at the plurality of memory cells as first bits, the second write data is selected as the CSB data to be written at the plurality of memory cells as second bits, and the third write data is selected as the MSB data to be written at the plurality of memory cells as third bits.
10. The operating method of claim 9, wherein the nonvolatile memory further comprises:
first latches, second latches, and third latches connected to the plurality of memory cells, respectively;
second memory cells connected to a same word line as the plurality of memory cells; and
fourth latches, fifth latches, and sixth latches connected to the second memory cells, respectively,
wherein the operating method further includes,
loading encoding data of the first write data on the first latches;
loading encoding data of the second write data on the second latches; and
loading encoding data of the third write data on the third latches.
11. The operating method of claim 10, further comprising:
respectively loading next encoding data on the fourth latches, the fifth latches, and the sixth latches, and then, writing the data loaded on the first to sixth latches at the plurality of memory cells and the second memory cells.
12. An operating method of a storage device which includes a nonvolatile memory including a plurality of memory cells; and a memory controller adapted to control the nonvolatile memory, the operating method comprising:
receiving write data to be written, as a plurality of data units, to the plurality of memory cells,
each of the plurality of data units corresponding to one of at least first through eighth threshold voltages,
each of the at least first through eighth threshold voltages corresponding to a different one of a plurality of multi-bit data values,
each of the multi-bit data values including a least significant bit (LSB), at least one central significant bit (CSB), and a most significant bit (MSB);
dividing the write data based on significance of bits of the write data;
encoding the write data by,
encoding LSB data, from among the write data,
encoding CSB data, from among the write data, based on LSB data corresponding to the CSB data, and
encoding MSB data, from among the write data, based on LSB data and CSB data corresponding to the MSB data.
13. The method of claim 12, wherein the encoding includes encoding the write data such that a number of data units, from among the plurality of data units, having a same multi-bit data value as a highest multi-bit data value is reduced,
the highest multi-bit data value being the multi-bit data value, from among the plurality of multi-bit data values, to which a highest threshold voltage state corresponds,
the highest threshold voltage state being a highest one of the at least first through eighth threshold voltage states.
14. The method of claim 12, wherein the CSB data includes a first plurality of CSBs and a second plurality of CSBs, and the encoding includes encoding the CSB data such that,
values of the first plurality of CSBs are changed based on,
a combination of the first CSBs and bits of encoding data of the LSB data corresponding to the first CSBs, and
values of the second plurality of CSBs are changed based on the second plurality of CSBs regardless of the encoding data of the LSB data.
15. The method of claim 12, wherein the MSB data includes a first plurality of MSBs and a second plurality of MSBs, and the encoding includes encoding the MSB data such that,
values of the first plurality of MSBs are changed based on,
a combination of the first MSBs, bits of encoding data of the CSB data corresponding to the first MSBs, and bits of encoding data of the LSB data corresponding to the first MSBs, and
values of the second plurality of MSBs are changed based on the second plurality of MSBs regardless of the encoding data of the LSB data and regardless of the encoding data of the CSB data.
16. The method of claim, 12, wherein the nonvolatile memory comprises a three-dimensional memory array which includes the plurality of memory cells.
17. The method of claim 16, wherein the three-dimensional memory array is monolithically forms in one or more physical levels of memory cells having active areas disposed above a silicon substrate.
18. The method of claim 16, wherein each of the memory cells includes a charge trap later.
19. The method of claim 16, wherein word lines andor bit lines in the three-dimensional array are shared between levels.
20. The method of claim 12, wherein the nonvolatile memory includes a plurality of strings arranged in rows and columns on a substrate,
wherein each string includes at least one select transistor and memory cells stacked on a direction perpendicular to the substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Sensor for measuring the partial pressure of a gas in a gaseous medium, of the type comprising an electrochemical cell (2) and a porous diffusion barrier situated upstream of said cell along the course of said gaseous medium, said diffusion barrier comprising a porous membrane (10) having very fine pores, situated above an orifice (7) made in a component surmounting a casing (1) enclosing said electrochemical cell (2), characterized in that it comprises:
a cap (3) surmounting said casing (1) in a leaktight manner, said cap (3) including or consisting of a first component (4) provided with a central recess (5) in the bottom of which said orifice (7) is made, a housing (9) being provided in the bottom (6) of said recess around said orifice (7) so as to place said porous membrane (10) therein;
a second component (11) applying said membrane (10) against the bottom (6) of said housing (9) with a clearance between said second component (11) and the lateral wall of the housing (9) permitting the passage of the gaseous medium to be analyzed toward said membrane (10); and
a third component (12) held in said central recess (5) of said first component (4) in such a way as to exert on said second component (11) the pressure required for the application of said membrane (10) against the bottom (6) of said recess (9), and comprising at least one orifice (13, 13) permitting the passage of said gaseous medium from outside the sensor up to said membrane (10).
2. Sensor according to claim 1, characterized in that said first (4), second (11) and third (12) components are made of a corrosion-insensitive metallic material exhibiting low expansion between 10 and 40 C., such as SUS 316L stainless steel.
3. Sensor according to claim 1 or 2, characterized in that said cap (3) comprises a polymer envelope laterally jacketing said first metal component, and in that said envelope (8) ensures leaktight contact between the cap (3) and the casing (1) enclosing the electrochemical cell (2).
4. Sensor according to one of claims 1 to 3, characterized in that the central recess (5) of the first component comprises a thread on its lateral wall, and in that the third component (12) comprises on its external wall a thread corresponding to the previous one, so as to ensure the securing together of the first (4) and third (12) components and the holding of the third component (12) in a position where it can ensure the application of the second component (11) against the porous membrane (10).