1. A memory device comprising:
a delay-locked loop circuit having a plurality of delay elements;
a synchronization circuit coupled to said delay-locked loop circuit and a synchronization enable signal, said synchronization circuit outputting a plurality of enable signals; and
an output circuit having a buffer coupled to a data input enable signal and a data output enable signal, said buffer circuit generating an output,
wherein said output circuit further comprises a data input pointer and a data output pointer.
2. The memory device of claim 1 wherein said delay-locked loop circuit receives an external clock signal.
3. The memory device of claim 1 further comprising a read circuit having a signal sense array.
4. The memory device of claim 3 wherein said synchronization circuit provides a first read enable signal to said read circuit.
5. The memory device of claim 3 wherein said synchronization circuit provides a second read enable signal to said read circuit.
6. The memory device of claim 1 further comprising a dynamic random access memory.
7. Memory device comprising:
a delay-locked loop circuit having a plurality of delay elements;
a synchronization circuit coupled to said delay-locked loop circuit and a synchronization enable signal, said synchronization circuit outputting a plurality of enable signals;
an output circuit having a buffer coupled to a data input enable signal and a data output enable signal, said buffer circuit generating an output; and
a data input pointer circuit coupled to receive said data input enable signal and a data output pointer circuit coupled to receive said data output enable signal.
8. The memory device of claim 7 further comprising a decoder coupled to receive an input pointer from said data input pointer circuit and generate an input address for said buffer.
9. The memory device of claim 8 wherein said decoder is further coupled to receive an output pointer from said data output pointer circuit and generate an output address for said buffer.
10. The memory device of claim 7 wherein said memory device comprises a dynamic random access memory.
11. A memory device comprising:
a delay-locked loop circuit having a plurality of delay elements;
a synchronization circuit coupled to said delay-locked loop circuit and a synchronization enable signal, said synchronization circuit outputting a plurality of enable signals;
an output circuit including a data input pointer circuit coupled to receive a data input enable signal from the plurality of enable signals and a data output pointer circuit coupled to receive a data output enable signal; and
a read circuit having a signal sense amplifier coupled to said synchronization circuit, said read circuit receiving a read enable signal from said synchronization circuit.
12. The memory device of claim 11 wherein the output circuit further comprises a buffer coupled to said synchronization circuit.
13. The memory device of claim 11 wherein said output circuit further comprises a decoder coupled to receive an input pointer from said data input pointer circuit and generate an input address for said buffer.
14. The memory device of claim 13 wherein said decoder is further coupled to an output pointer from said data output pointer circuit and generate an output address for said buffer.
15. A memory device comprising:
a delay-locked loop circuit having a plurality of delay elements, said delay-locked loop circuit generating a plurality of delayed clock signals;
a synchronization circuit coupled to said delay-locked loop circuit and receiving said plurality of delayed clock signals and a synchronization enable signal, said synchronization circuit outputting a data output enable signal; and
an output circuit having a buffer coupled to said synchronization circuit, said buffer circuit generating an output in response to said data output enable signal.
16. The memory device of claim 15 further comprising a read circuit having a signal sense amplifier coupled to said synchronization circuit, said read circuit receiving a read enable circuit from said synchronization circuit.
17. The memory device of claim 16 wherein said read enable circuit is based upon the synchronization enable signal and a delayed clock signal.
18. The memory device of claim 16 wherein said read circuit comprises a signal sense array coupled to a plurality of bit lines of said memory device.
19. A memory device comprising:
a delay-locked loop circuit having a plurality of delay elements, said delay-locked loop circuit generating a plurality of delayed clock signals;
a synchronization circuit coupled to said delay-locked loop circuit and receiving said plurality of delayed clock signals and a synchronization enable signal, said synchronization circuit outputting a plurality of enable signals;
a read circuit comprising a signal sense amplifier, said read circuit receiving a read enable signal; and
an output circuit coupled to said synchronization circuit, said output circuit receiving a data input enable signal enabling the storage of data in a buffer circuit and a data output enable signal enabling the output of data from said buffer circuit.
20. A method of reading data from a memory device, said method comprising:
coupling an external clock signal to a delay-locked loop circuit;
generating a plurality of delayed clock signals based upon said external clock signal;
coupling a synchronization enable signal to a synchronization circuit;
generating a read signal based upon said synchronization enable signal and a first delayed clock signal in the plurality of delayed clock signals of said external clock signal; and
synchronizing a data output enable signal to said read signal.
21. The method of claim 20 further comprising a step of generating a data input enable signal based upon said synchronization enable signal and a second delayed clock signal.
22. The method of claim 20 further comprising a step of generating a data output enable signal based upon said synchronization enable signal and a third delayed clock signal.
23. The method of claim 20 wherein said step of generating a data output enable signal comprises a step of generating a data output enable signal which is synchronized to said read signal.
24. A method of reading data from a memory device, said method comprising:
coupling an external clock signal to a delay-locked loop circuit;
generating a plurality of delayed clock signals based upon said external clock signal;
coupling a synchronization enable signal to a synchronization circuit;
generating a read signal based upon said synchronization enable signal and said external clock signal; and
generating a data output enable signal based upon said synchronization enable signal and said external clock.
25. The method of claim 24 further comprising a step of generating a data input enable signal based upon said synchronization enable signal and a second delayed clock signal.
26. The method of claim 24 wherein said step of generating a data output enable signal comprises generating a data output signal which is synchronized with said read signal.
27. The method of claim 24 further comprising a step of reading data from a dynamic random access memory.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An image heating apparatus comprising:
a heat member that heats an image on a recording material;
a pressure member that forms a nip portion for pinching and conveying the recording material with the heat member;
a first temperature detection element that detects a temperature of the heat member in a region for feeding a recording material having the smallest size which can be used by the image heating apparatus, in a direction perpendicular to a conveyance direction of the recording material;
a second temperature detection element that detects a temperature of the heat member in a region outside of the region for feeding the recording material having the smallest size in the direction perpendicular to the conveyance direction of the recording material; and
a control part that controls power supplied to the heat member, wherein in a heat process period in which the image is heated by the nip portion, the control part controls the power supplied to the heat member such that a temperature detected by the first temperature detection element keeps a target temperature,
wherein in a warm-up period in which the power is supplied to the heat member so that the temperature of the heat member reaches the target temperature, in a case where the temperature detected by the second temperature detection element is higher than the temperature detected by the first temperature detection element, the control part controls the power supplied to the heat member so that the temperature detected by the second temperature detection element reaches the target temperature, and until the temperature detected by the first temperature detection element reaches the target temperature after the temperature detected by the second temperature detection element reaches the target temperature, the control part controls the power supplied to the heat member so that the temperature detected by the second temperature detection element keeps the target temperature.
2. An image heating apparatus according to claim 1, wherein the heat member includes a heating film and a heater arranged in contact with an inner surface of the heating film, and the nip portion is formed by the heater and the pressure member via the heating film.