1. A semiconductor device, comprising:
a substrate having transistor devices and a passivation layer disposed over a dielectric layer that is defined over the transistor devices;
a plurality of copper interconnect metallization lines and conductive vias defined in each of a plurality of interconnect levels of the semiconductor device, the plurality of copper interconnect metallization lines and conductive vias being isolated from each other by a porous dielectric material; and
a plurality of supporting stubs, each of the plurality of supporting stubs configured to form a supporting column that is disposed over a surface of the passivation layer and extends through the plurality of interconnect levels of the semiconductor device, the plurality of supporting stubs not being electrically interconnected to the plurality of copper interconnect metallization lines and conductive vias so that the supporting column maintains structural contact with the passivation layer to avoid electrical contact with the plurality of copper interconnect metallization lines and conductive vias, the plurality of supporting stubs further being configured so as to not provide electrical connection between the plurality of interconnect levels of the semiconductor device.
2. The semiconductor device as recited in claim 1, further comprising:
a passivation-capping layer defined over a topmost layer of the copper interconnect metallization lines and conductive vias.
3. The semiconductor device as recited in claim 1, wherein the plurality of copper interconnect metallization lines and conductive vias define dual damascene structures.
4. The semiconductor device as recited in claim 1, wherein the plurality of supporting stubs further support a passivation-capping layer.
5. A semiconductor device, comprising:
a substrate having transistor devices;
an intermetal dielectric layer (ILD) including conductive contacts defining a first interconnect level of a plurality of interconnect levels of the semiconductor device;
a passivation layer defined over the ILD layer;
a plurality of copper interconnect metallization lines and conductive vias defined in each remaining interconnect level of the plurality of interconnect levels of the semiconductor device defined over the passivation layer, the plurality of copper interconnect metallization lines and conductive vias being isolated from each other by only a porous dielectric material; and
a plurality of supporting stubs, each of the plurality of supporting stubs configured to form a supporting column that extends through each remaining interconnect level of the plurality of interconnect levels of the semiconductor device.
6. The semiconductor device as recited in claim 5 wherein the plurality of supporting stubs is not electrically interconnected to the plurality of copper interconnect metallization lines and conductive vias.
7. The semiconductor device as recited in claim 5, wherein the plurality of supporting stubs further support a passivation-capping layer.
8. A semiconductor device, comprising:
a substrate having transistor devices;
an intermetal dielectric layer (ILD) including conductive contacts defining a first interconnect level of a plurality of interconnect levels of the semiconductor device, the conductive contacts being isolated from each other by a non-porous dielectric;
a passivation layer defined over the ILD layer;
a plurality of copper interconnect metallization lines and conductive vias defined in each remaining interconnect level of the plurality of interconnect levels of the semiconductor device, the plurality of copper interconnect metallization lines and conductive vias being isolated from each other by one of only a porous dielectric material and a mixture of only a porous dielectric material and a gaseous dielectric;
a passivation-capping layer defined over a topmost layer of the copper interconnect metallization lines and conductive vias; and
a plurality of supporting stubs, each of the plurality of supporting stubs configured to form a supporting column that extends through each remaining interconnect level of the plurality of interconnect levels of the semiconductor device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-26. (canceled)
27. A method for delivering a donor polynucleotide to a double-stranded break at a target site, comprising:
contacting a DNA sequence comprising the target site with an engineered nucleic acid targeting nucleic acid comprising a crRNA and tracrRNA wherein (i) the engineered nucleic acid targeting nucleic acid is associated in a complex with a Cas9 protein to form a crRNA-tracrRNA-Cas9 complex, (ii) the tracrRNA comprises a 3\u2032 end, (iii) the tracrRNA further comprises a hybridizing sequence at the 3\u2032 end, (iv) the hybridizing sequence comprises a nucleic acid sequence that hybridizes to the donor polynucleotide, and (v) the crRNA-tracrRNA-Cas9 complex binds to the DNA sequence comprising the target site and cuts the target site to generate a double-strand break and the binding of the crRNA-tracrRNA-Cas9 complex delivers the donor polynucleotide to the double-stranded break at the target site.